dco clock stability

Enzo Ternavasio said:

I have set a high clok frequency on MSP430F5171 (30MHz), using DCO, that is not exactely that value.

Well, 30MHz is far outside the specs. Even though it is possible to run the DCO at this speed, there is no way to get this frequency out of the MSP (only divided)

However, how did you 'set 30MHz'?

Enzo Ternavasio said:

What i need to know is if a series production based on this micro should have the same base frequency or i have to expect a spread of values.  I have not found this on data sheet.

Reading data sheet it seems that stability changes only with temperature and Voltage.

No. even at a given temperature and voltage, there is a (wide) spread across different devices. If oyu look at the table in the datasheet, you'll see for a specific DCOx/RSELx setting a quite large frequency range. This variation is not only due to temperature and voltage range. If you do some math, you'll see that the range is wider than it could be with those two factors alone.
Also, teh datasheet specifies the drift only for 1MHz frequenc. On other DCO frequencies, it might be different.

This is the main reason for introducing an FLL that adjusts the DCO based on a stable reference clock.

Jens-Michael Gross said:

Well, 30MHz is far outside the specs. Even though it is possible to run the DCO at this speed, there is no way to get this frequency out of the MSP (only divided)

Yes, it is out of spec for sure, but I (and others) was able to push it much higher (48 MHz with XT2, 56 MHz with DCO), and measured correct MCLK on P4 (PM_MCLK) pin.

http://forum.43oh.com/topic/3906-msp430f5xx-overclocking

Hy Jens,

i set 30 MHz in this way:

void clock(void)
{
SetVcoreUp (0x01);
SetVcoreUp (0x02);
SetVcoreUp (0x03);

// configure clocks
UCSCTL3 = SELREF_2; // Set DCO FLL reference = REFO
UCSCTL4 |= SELA_2; // Set ACLK = REFO error +/- 1.5%

__bis_SR_register(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_7; // Select DCO range 50MHz operation
UCSCTL2 = FLLD_1 + 915; // Set DCO Multiplier for 19.0MHz
// (N + 1) * FLLRef = Fdco
// (915 + 1) * 32768 = 30.0MHz
// Set FLL Div = fDCOCLK/2
__bic_SR_register(SCG0); // re-enable the FLL control loop

__delay_cycles(782000);

// Loop until XT1 fault flag is cleared
do
{
UCSCTL7 &= ~(XT1LFOFFG + XT1HFOFFG+ DCOFFG);
// Clear XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while (SFRIFG1&OFIFG); // Test oscillator fault flag
}

In data sheet are reported DCO frequencies far beyond 30MHz.

Anyway i will use an external oscillator, that will provide the stability requested.

Enzo