ossible to generate a PWM signal with 100% Duty Cycle using MSP430G2231.

Set your output pin of choice high.

I have a even simpler scheme.

Indeed. Good job.

Well that was easy, but is there way to set PWM to 110% without resorting to time warping ?

P

To challenging for engineers. But easy for marketing professionals.

Seriously, if you use a Timer in the up-mode, CCRn for duty-cycle and CCR0 for period to generate PWM, this is what you can get: (Assuming CCR0 = 100-1;)

CCR1 = 0 generates 0% duty-cycle.
CCR1 = 1 generates 1% duty-cycle.
CCR1 = 2 generates 2% duty-cycle.
…
CCR1 = 99 generates 99% duty-cycle.
CCR1 >= 100 generates 100% duty-cycle.

Hi All,

Thanks for your help.

I need to generate A PWM  with 100% Duty Cycle for 600mS ,for next 7S Duty Cycle will be 50 %  .

Guide me on that

The three terms PWM, Duty Cycle and 100% are mutually exclusive.

If you have a PWM with a duty cycle, it has a PWM frequency. If you have a duty cycle of 100%, it has no frequency.

Besides this, the MSP is of course able to generate a static output signal. Even by teh mechanisms that are usually used for a 100% (or 0%) 'Duty cycle'.

Usually, you operate the timer in up mode, set the cycle length in CCR0 and the duty cycle in CCRx as a percentage of the CCR0 value.

And depending on polarity, you use set/reset ot reset/set output mode.

If you now set CCRx to a value > CCR0, the timer will never reach it, as it reaches CCR0 earlier and resets to 0. So in reset/set mode, the output will set on TAR->0 but never reset, as TAR will never reach CCR1 ().

utpal kumar said:

I need to generate A PWM  with 100% Duty Cycle for 600mS ,for next 7S Duty Cycle will be 50 %  .

Take a flashing LED example code and increase the flashing frequency to generate desired PWM.

Add an outside loop similar to the flashing LED example.

You are done.

Peter

utpal kumar said:

I need to generate A PWM  with 100% Duty Cycle for 600mS ,for next 7S Duty Cycle will be 50 %  .

Guide me on that

Easy. OCY's approach is a novel method. Use another timer (say, with 100ms resolution on the interrupt) to control the timing of the different phases of your output waveform (on for .6s, 50% for 7s) and in that control loop set the CCRx appropriately.

old_cow_yellow said:

CCR1 = 0 generates 0% duty-cycle.

If CCR1 is 0, both, set and reset happen at the same time (TAR->0 and TAR->CCR1 are both true). For the 3x family, this condition was defined in teh users guide, but in all othe rfamilies, it is not state which case takes precedence.
So it may or may not work, and even if it works (it apparently does), it might stop working on next silicon revision.
So if relying on it, this should be on the re-test list for new silicon revisions.