MSP430 UART Interrupts: USCIAB0RX_VECTOR,USCIAB0TX_VECTOR

Hello,

i'm wondering when the two ISR are triggered:

USCIAB0TX_VECTOR

USCIAB0RX_VECTOR

Couldn't find any Information about that.

Thank you.

Its about that example of MSP430Ware for MSP430F2132 msp430x21x2_uscib0_i2c_11, this is the I2C Slave Code. The Slave is transmitting 5 Bytes.

#include <msp430.h>

unsigned char *PTxData; 
volatile unsigned char TXByteCtr;
const unsigned char TxData[] = 
{
0x11,
0x22,
0x33,
0x44,
0x55
};

int main(void)
{
  WDTCTL = WDTPW + WDTHOLD; // Stop WDT
  P3SEL |= 0x06; // Assign I2C pins to USCI_B0
  UCB0CTL1 |= UCSWRST; // Enable SW reset
  UCB0CTL0 = UCMODE_3 + UCSYNC; // I2C Slave, synchronous mode
  UCB0I2COA = 0x48; // Own Address is 048h
  UCB0CTL1 &= ~UCSWRST; // Clear SW reset, resume operation
  UCB0I2CIE |= UCSTPIE + UCSTTIE; // Enable STT and STP interrupt
  IE2 |= UCB0TXIE; // Enable TX interrupt

while (1)
{
  PTxData = (unsigned char *)TxData;
  TXByteCtr = 0;
  __bis_SR_register(CPUOFF + GIE); 
  __no_operation(); 
} 
}

#pragma vector = USCIAB0TX_VECTOR
__interrupt void USCIAB0TX_ISR(void)
{
UCB0TXBUF = *PTxData++; // Transmit data at address PTxData
TXByteCtr++; // Increment TX byte counter
}

#pragma vector = USCIAB0RX_VECTOR
__interrupt void USCIAB0RX_ISR(void)
{
UCB0STAT &= ~(UCSTPIFG + UCSTTIFG); 
if (TXByteCtr) 
__bic_SR_register_on_exit(CPUOFF); 
}