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Highest Clock Frequency Available on MSP430F2012

Other Parts Discussed in Thread: MSP430F2012

Hi all,

I was wondering if anyone who has used the MSP430F2012 knows the kinds of high frequencies that I can set up for a USI I2C bus protocol. I want to try high speed mode, which is a max of 3.4 MHz (compared to 400 kHz in fast mode), and I have always only used as a source clk of at most 1 MHz, so I was wondering if anyone knew how to set up a higher clock frequency. This setup is done in USI by coding something along the lines of:

USICKCTL = USIDIV_3+USISSEL_2+USICKPL; // Setup USI clocks: SCL = SMCLK/8 (~120kHz)

It seems like if SMCLK is the highest frequency of ~1MHz, then I can only make it smaller with the USIDIV_3, not bigger. Is SMCLK the highest-frequency clock that I can use on the MSP430F2012? Any help would be greatly appreciated!

Thanks,

Matt

  • First you shall read MSP430F2012 datasheet yourself. If still have questions - then unfortunately you shall come and ask again.

  • Ok, so I found the DCO calibration data (1MHz, 8Mhz, 12MHz, 16MHz), but I can't figure out which clocks it refers to. I believe it at least refers to SMCLK, but can I use those calibration registers to set ACLK or SCLK?

  • DCO calibration data refers to DCO oscillator. Now you shall read msp430x2xx series user manual, clocking subsystem chapter to understand how DCO oscillator freq relates to MCLK, SMCLK and ACLK, how you can change this relation.

  • Thanks,

    I have it set to the 16MHz speed, and then set up my USI SCL for I2C like this:

    BCSCTL1 = CALBC1_16MHZ;
    DCOCTL = CALDCO_16MHZ;

    ...


    USICKCTL = USIDIV_1 + USISSEL_2 + USICKPL; // USI clks: SCL = SMCLK/2

    When I use USIDIV_1 (divide it by 2^1), I only get see a clk frequency of ~720 kHz. When I use USIDIV_0 (divide it by 2^0), I do not see a clk frequency at all. Do you have any insight as to why that is?

  • Matthew Wasko said:
    I do not see a clk frequency at all.

    What tool do you use to measure it? If 24MHz "logic analyzer", then right now start looking for scope ;)

  • Matthew Wasko said:
    When I use USIDIV_1 (divide it by 2^1), I only get see a clk frequency of ~720 kHz.

    Show what you do with all BCSCTL registers, are you sure you don't alter BCSCTL2, especially DIVSx?

    Or just:

    P1DIR |= 0x10; // P1.4 outputs
    P1SEL |= 0x10; // P1.4 SMCLK output

    measure freq on P1.4

  • I checked P1.4 and got the right frequencies if I changed the DCO calibration to 1 MHz or 16 MHz. However, my SCL for the I2C bus protocol (P1.6), which I thought I set based on SMCLK (which I though is based on the DCO) gives me the 720 KHz or no clk readings. Did I make the right assumptions about how SCL being related to SMCLK as well as how SMCLK is related to DCO?

  • Matthew Wasko said:
    how SMCLK is related to DCO?

    I already said - read user manual, it's written there.

    Matthew Wasko said:
    gives me the 720 KHz

    First - how you measure 720KHz. Are you sure your tool or method measure freq correctly? Please show scope waveform.

    Matthew Wasko said:
    or no clk readings.

    Your pull-up simply can be too weak giving too slow rise time for such a fast clock resulting clock line never reaching logic "1". THat's why I said - look at clock line with scope. Probably you did not hear that.

  • I read the manual. And here is an image of my SCL line:

    This is running with DCO at 1MHz and I set the SCL signal up with this: USICKCTL = USIDIV_1 + USISSEL_2 + USICKPL;      // USI clks: SCL = SMCLK/2.

    This makes me think that the signal should be 500kHz, however, its period as seen in the waveform is 4.985 us which means about 200 kHz.

    This is the same oscilloscope and probes that I used to measure that the DCO on P1.4 was properly at 1MHz and 16MHz when I changed it. It shouldn't matter that this is trying to technically run at 500kHz which is over the limit for I2C fast speed mode (400kHz) because it is the master, right?

    Matt

     

  • Also, P1.4 makes a nice square wave, however this image above shows a shark-fin looking waveform. Does the 'bad' shape of the waveform correlate to the incorrectness of my expected frequency? Or does it have to do with the fact that I am on the SCL line/trying to run USI I2C?

    Thanks,

    Matt

  • Even at 200KHz your clock rise time is too slow. I already said - your pull-up is too weak. Resistor between SCL and VCC shall have smaller resistance.  No wonder you can't run faster clocks because at 200KHz clock waveform already looks sick. Try extreme like 2k2 pull-up.

  • Ok, I can do that. If youre still there, I am having trouble reading P1.4 again. I took the code that matters and put it into main:

    int main(void)
    {
    WDTCTL = WDTPW + WDTHOLD; // Stop watchdog
    BCSCTL1 = CALBC1_1MHZ; // Set DCO
    DCOCTL = CALDCO_1MHZ;
    //P1OUT = 0xC0; // P1.6 & P1.7 Pullups, others to 0 // I ALREADY TRIED WITH THESE COMMENTED LINES BACK IN, IT STILL DOESN"T WORK LIKE THIS
    //P1REN |= 0xC0; // P1.6 & P1.7 Pullups
    //P1DIR = 0xFF; // Unused pins as outputs
    //P2OUT = 0;
    //P2DIR = 0xFF;
    P1DIR |= 0x10; // P1.4 outputs // PIN 6
    P1SEL |= 0x10; // P1.4 SMCLK output
    while(1);
    }

    When I probe P1.4 with this code, I get this:

    The frequency is correct at almost 1 us, but It is a very small signal. Am I missing something here? I just added those two lines back in that you told me before (i had it at the correct voltage before, I must have changed something on accident).

    Thanks so much!

    Matt

  • Matt, how did you became TI emplyee? Maybe try KFC? [joke]

    Matthew Wasko said:
    Am I missing something here?

    I can't see from here. You have to look at your circuit yourself.

  • Haha, I got it working. Thanks!

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