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DSPI with msp430 family G2553

Jonathan Takacs
Prodigy 20 points

Hey,

Working on interfacing an MSP430 with offboard memory that uses a DSPI (they call it dual serial perf. Interface) connection.

I'm looking at chapter 16.3 of the user guide, and I'm looking for direction on interfacing this device. 

DSPI by my parts datasheet expects the data to be interleaved and It seems to be half duplex. The first 16 bits are sent on the first 8 clock cycles, with the first two bits on cycle one sent on d0 and d1 (the two SPI data lines) in one direction During this chip select is high and the clock is pulsing making this a 4 wire interface. These first 16 bits are referred to as the instruction word which contains the physical address to write to on the external memory along with opcodes and other assertions. There is then a pause and the next 8 clock cycles send 16 bits of data to the addressed memory location.

My question is does the device I'm using support such a protocol natively or will I have to implement support in software? My I be directed to any resources? 

  • 0
    TI__Guru 63850 points

    The serial interfaces on the MSP430 family of devices do not support multiple lanes of data, only 1 in each direction.

    Therefore, I believe you will need to implement such a protocol through software manipulation of digital I/O.

  • 0
    Guru 227245 points

    Jonathan Takacs said:
    My question is does the device I'm using support such a protocol natively or will I have to implement support in software?

    As Brandon said, the MSP doesn't support it in hardware. You may do it in software using standard software-controlled IO. However, my guess is that a hardware uspported single-lane SPI will be faster than a software-implemented multi-lane SPI - unless you have a whole bunch of lanes (e.g. 8 bit parallel).

  • 0 in reply to Jens-Michael Gross
    Prodigy 20 points

    Jens-Michael Gross said:

    My question is does the device I'm using support such a protocol natively or will I have to implement support in software?

    As Brandon said, the MSP doesn't support it in hardware. You may do it in software using standard software-controlled IO. However, my guess is that a hardware uspported single-lane SPI will be faster than a software-implemented multi-lane SPI - unless you have a whole bunch of lanes (e.g. 8 bit parallel).

    [/quote]

    I think the issue is the device requires this. The device I am using does have two SPI controlers, and it has crossed my mind as you are suggesting to use those hardware devices to interleave the data as the external device requires. 

    the device uses just 4 lanes, just like standard SPI except the two lines for a full duplex communication are instead used to increase throughput by interleaving bits. i.e. you are sending twice the data one way per clock cycle by sacrificing two way communication.

    So Jens, what you are saying is I could have the d0 and d1 lines for the external device attached two the output lanes of the two SPI controlers. After I transulate the bytes to binary I wish to send in software, I could then shift out odd then even bytes to the SPI controlers on clock edges at same time to implement the protocol. This way I keep the protocal yet get the speed and buffer advantages of using native hardware?

  • 0 in reply to Jonathan Takacs
    Guru 227245 points

    Jonathan Takacs said:
    So Jens, what you are saying is I could have the d0 and d1 lines for the external device attached two the output lanes of the two SPI controlers.


    There is a way to do it. You would have to program one SPI as master, one as slave. The clock form the master goes into the slave SPI.
    Phase must be different for the slave than for the master. THen you feed the even bits for 2 bytes(!) into one of htem and the odd bits into the other. Write to the slave first. Once you write to the master, transfer begins.

    But with the additional effort of splicing the bits (and joining them on the input, as well as switching port pin directions between send and receive), this will likely take as much time as doing all this in software. SO I'm not sure it is worth the effort.

    An alternative would be an external hardware that gets the SPi date seriall on one lane and splices it to two lanes, stretching the clock signal. A few D-flipflops should do. But likely not worth the effort.

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