MSP430 ARCHTECTURE

Why don't you use internet search first? This popped-up as one of first google offers:

You can find answer in this page: http://www.ti.com/lsds/ti/microcontroller/16-bit_msp430/getting_started.page

High Performance 16-bit Architecture. A 16-bit RISC CPU, peripherals and flexible clock system are combined by using a von-Neuman common memory address bus (MAB) and memory data bus (MDB). Partnering a modern CPU with modular memory-mapped analog and digital peripherals, the MSP430 offers solutions for today and tomorrow's mixed-signal applications.

Hi,

 I have a query on the following statement,

Ilmars said:

A 16-bit RISC CPU, peripherals and flexible clock system are combined by using a von-Neuman common memory address bus (MAB) and memory data bus (MDB).

As per my understanding in von-Neuman architecture uses a single bus for address and data fetching from the memory. Then in MSP architecture MAB and MDB buses used, i have little bit confusion in this.

Can any one explain what is it exactly?

Thanks

The key word is "common".

Prakash Balagangatharan said:

Can any one explain what is it exactly?

Anyone who reads the user's guides can explain it to themselves. The architecture is talked about in the documentation. Spend some time and do the research.

Here.... I'll even throw you another bone: Section 1.1 of SLAU144

Prakash, von-Neumann structure means that data and instructions are fetched through the same 'bus' (even though data signals and address signals usually use separate traces, also called data bus and address bus, but sometime smultiplexed), so data memory and instruction memory are the same. Harvard uses two separate buses (each one being an address bus and data bus pair or multiplexed), so you cannot read data from program memory or execute code from data memory. However, you can read the next instruction while writing the result of the last.

Thanks Jens,

       I need  the clarification for the statement which has been quoted below

Jens-Michael Gross said:

It has nothing to do with using a multiplexed address and data bus (where you first send the address through the lines,

As per this shall i assume memory address bus is nothing but multiplexed address bus.

Thanks in advance

The term ‘bus’ has two different meanings.

First, there is the physical bus. It consists of several parallel data lines and some control signal lines. Where ‘data’ here means the information the bus carries.

Talking about data and address bus, this means two physical bus systems. One transports the address information to a peripheral, while the other transports the data information from or to the peripheral. Depending on the implementation, address bus and data bus can share the same signal lines (multiplexed bus). In this case, first the address information is sent (signaled by the control lines) and latched in the peripheral, then the data is sent (or received) in a second transfer cycle.

The other usage is the functional bus. The functional code memory bus of a CPU is a connection between the CPU and its memory, where it fetches its instructions from. This logical bus consists of a physical address bus and a physical data bus. (on more complex CPUs, there can be multiple such address/data bus pairs, to allow parallel access to multiple memory chips).
The functional data memory bus is a connection between the CPU and the storage place for its data. It again consists of an address bus and a data bus.

In Harvard architecture, the code memory bus and the data memory bus are separate. So data goes to data memory and code comes from code memory. Data cannot be read from code memory and code cannot be executed from data memory. The advantage is that the CPU can read its next instruction and store the result of the current instruction at the same time, as it goes through two different physical signal systems to two different memory chips. The disadvantage is that you can’t alter code memory by a program. So it is practically impossible to implement an OS that dynamically loads code from mass storage and executes it.
Well, some systems like the ATMega have circumvented it by introducing CPU instructions that do data read and write access to code memory (violating the Harvard concept). However, those instructions are slow. And the instruction used determines whether an address points to code or data memory (the same address exists twice in the address range)

So a physical bus can use multiplexed address and data lines (smaller), or not (faster) to access a peripheral (e.g. memory).