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Can the MSP430G2x13 be configured as an I2C Slave Monitor?

Hello, 

I need to add a monitor to an existing I2C bus (Master and Slave 1), to read data from the master/slave.
Can the MSP430G2x13 act as a Slave Monitor (Slave 2), which only receives data on I2C bus, but never responds with ACK?

I read through the user's guide. The I2C module on MSP430G2x13 can be configured as Slave Transmitter or Slave Receiver, but neither of them can act as a "monitor", because both send acknowledge to the master.

- Can the MSP430G2x13 be configured as an I2C Slave Monitor? How? (Fig.1)
- If not, will it work by modifying the SDA wire to single-direction? (Fig.2)

  • The G2x13 has an USCI module that is a full-features I2C master/slave unit. Not, it can't work as I2C monitor in hardware.
    But of course you can monitor the I2C signal lines in software through plain GPIO.

    An MSP with an USI module could be programmed to just monitor the I2C traffic but never send anything. The USCI cannot.

  • Thank you Jens.

    It is the MSP430G2x13 in my previous project and I hope to use the existing model.
    It seems that the only way is to BLOCK the auto-acknowledgement from the G2x13 (Slave 2).
    Does a logic gate work here?

  • With this trick, you could indeed detect whether the master has addressed the slave, and also read anything th emaster sends to the slave. However, you won't be able to listen to what the slave might send to the master as in this case the MSP would also trying to send to the master and not listen. Also, if you don't handle teh fake transfer on the MSP  properly, the MSP could block SCL, stalling the bus.

    Also, in your schematics, you have the supply signs wrong. The bar is the sign for GND while the triangle indicates a supply voltage. So you're pullignthe bus low and always have the OR gate output active. :)

  • Jens,

    So far I just need to listen all data sent by the master and don't care about the responce of the slave.

    I used to draw schematics with Altium Designer and it use the bar sign for supply. 

    Again, thanks for your kind advice! :)

  • Need help, Jens.

    In your reply you said "if you don't handle teh fake transfer on the MSP properly, the MSP could block SCL, stalling the bus". Now I come with this problem! I configure the MSP as Slave 2, with own address same as Slave 1, and add the OR gate as Fig.3 above.

    When the Master starts to send date to Slave 1, it seems that Slave 2(the MSP) can only received ONE byte, and then it holds the SCL low and nothing going on the bus. Meanwhile, the UCSCLLOW bit of register UCB0STAT is set, indicating the SCL is held low.

    How to avoid stalling the bus?

  • Indeed, you must fetch the bytes from RXBUF in time, or the bus will stall.
    Same for the sending. Even though the monitor will not really send anything, if it sees a send request form the master, it will try to send, and when you do not provide the required (dummy) data, it will stall the bus.

    You must act as if the monitor slave would be the real slave.

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