Why some pins are active low and few are active high. Why not everything be active high in all the pins?
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Why some pins are active low and few are active high. Why not everything be active high in all the pins?
deepak murali said:Why some pins are active low and few are active high. Why not everything be active high in all the pins?
What you are talking about? Please provide part number specifying which pins are "active high" or "active low" in your understanding.
Right. Mostly.Ilmars said:Those "active" low inputs can be pulled low using open collector by more than one chip - that's the main reason why signals happen to be active low.
Back in TTL times, inputs did have internal pullups. So if idle, a line was high by default and had to be pulled actively low.
While in normal logic understanding, '1' means 'on' or 'active', data lines were usually driven high or low by the transmitter when data was sent. So the 'idle' state was unimportant. /If there is nobody sending, then the state of the data line is a don't care) On control lines, however, the idle state was important. They are usually made active low so that they ar einactive when there is nobody controlling this line.
As a side effect (or sometimes intentionally, like on I2C), multiple masters can control such an active-low line without fighting each other, by pulling it low with an open-collector output. (for some reasons, I think because of possible problems with base currents and supply voltages, and the said inherent pullup on the inputs, the open-emitter pendant wasn't used very often)
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