slave SPI very strange issue

You should post your code. Especially the USCI initialization, but if possible (and not too much) also the rest of the related code. Port pin setup, clock initialization, ISRs etc.

Mich said:

=> Why the TX internal state machine shifts 1 bit on each UCB0CLK when the STE pin is not active?

Do you use 4-wire mode? If not, STE has no meaning.

Mich said:

=> Why UCSWRST does not fully reset the USCI???

No idea. It should. However, some combinations of static signal level and clock polarity and phase may cause the shift register to 'receive' a bit as soon as SWRST is released. Check the phase and polarity settings.Some mismatched combinations between master and slave seem to work but not reliably (due to racing conditions)

Mich said:

=> Why the reset pin does not fully reset the USCI ???????

Perhaps for the same reason. Maybe the USCI is reset properly, but as soon as reset is released...

Thanks a lot for the answer. An other information: transfer is between 2 MSP430F247: one acts as master and the second acts as slave. The goal is to re-play recorded data from a uSD.

Jens-Michael Gross said:

You should post your code. Especially the USCI initialization, but if possible (and not too much) also the rest of the related code. Port pin setup, clock initialization, ISRs etc.

Both MSP430F247 have the same SPI configuration for clock polarity:

Master:

    UCB0CTL1 = (UCSSEL1 | UCSWRST); // SMCLK, UCMODE=0, reset
    UCB0CTL0 = (UCCKPL | UCMSB | UCMST | UCSYNC); // 8-bit, UCMSB, Master, UCMODE=0, sync
    UCB0BR0 = 0x002; // SPICLK = SMCLK/2 (2=Minimum divisor)
    UCB0BR1 = 0x000;
    UC0IFG &= ~(UCB0RXIFG | UCB0TXIFG); // reset IT flags
    UCB0CTL1 &= ~(UCSWRST); // SPI enable

Slave initialisation:

    P3DIR |= 0x04;
    P3SEL |= 0x0F;
    UCB0CTL0 = (UCCKPL | UCMSB | UCMODE_2 | UCSYNC); // 8-bit, UCMSB, slave, UCMODE=10, sync
    UCB0CTL1 &= ~(UCSWRST); // SPI enable
    UC0IFG &= ~(UCB0RXIFG | UCB0TXIFG); // reset IT flags

Slave SPI reset when a read access with 1st byte is 0x8F. This reset is done after the STE rising edge and I expected this reset to solve the slave issue (so a 2nd read from the master could be ok but this SPI reset does change anything)

        TEST61_ON;   // to confirm SPI reset on the oscilloscope
        //re initialize the SPI
        UCB0CTL0 = (UCCKPL | UCMSB | UCMODE_2 | UCSYNC); // 8-bit, UCMSB, slave, UCMODE=10, sync
        UCB0CTL1 &= ~(UCSWRST); // SPI enable
        UC0IFG &= ~(UCB0RXIFG | UCB0TXIFG); // reset IT flags
        UCB0TXBUF = 0x33;
        // autorise les it rx
        IE2 |= UCB0RXIE;                  // Enable Rx interrupts
        TEST61_OFF;

Jens-Michael Gross said:

Do you use 4-wire mode? If not, STE has no meaning.

4 wires

Jens-Michael Gross said:

=> Why UCSWRST does not fully reset the USCI???

No idea. It should. However, some combinations of static signal level and clock polarity and phase may cause the shift register to 'receive' a bit as soon as SWRST is released. Check the phase and polarity settings.Some mismatched combinations between master and slave seem to work but not reliably (due to racing conditions)

[/quote]

I am just realizing that I do not reset the SPI on the rising edge of STE (STE is link to another GPIO to permit this interrupt). In fact I copy the initialisation code where UCSWRST is already active after device reset. => I will check again if I can re-produce it.

UCB0CTL1 |= UCSWRST; is missing