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SPI clock divider

Rafid Karim
Prodigy 30 points
Other Parts Discussed in Thread: MSP430F5437A

Hi everybody, I'm working on a small project on the side using the MSP430f5437a.

I an new to MSP430 and have a question about the SPI setup. I'm trying to connect the MSP430 to the NFC shield v1.0 by seedstudio.

I'm having troubles with the connection and might think there is a problem with my setup of the clock. The NFC shield runs at a maximum of 5MHz so I divided the SMCLK(8MHz) by 2 to get 4 MHz, but the oscilloscope shows the same clock signals as the Ethernet at 8MHz. Is there an error in my code for the SPI initialize?

// RF SPI port
#define RF_SIMO            BIT6
#define RF_SOMI            BIT7
#define RF_SPI_IN        P5IN
#define RF_SPI_OUT        P5OUT
#define RF_SPI_DIR        P5DIR
#define RF_SPI_REN        P5REN
#define RF_SPI_SEL        P5SEL

#define RF_SCLK            BIT6
#define RF_SPI_SCLK_DIR    P3DIR
#define RF_SPI_SCLK_SEL    P3SEL

void spi_initialize(void) {
    // Activate reset state
    UCA1CTL1 |= UCSWRST;

    // Configure ports
    RF_SPI_SEL |= RF_SIMO + RF_SOMI; // Special functions for SPI pins, SIMO, SOMI
    RF_SPI_SCLK_SEL |= RF_SCLK;    // Special functions for SPI pins, SCLK

    RF_SPI_DIR |= RF_SIMO;    // Outputs, SIMO
    RF_SPI_SCLK_DIR |= RF_SCLK; //Outputs, SCLK

    UCA1CTL1 |= UCSSEL_2;                // SMCLK (8MHz) clock source
    UCA1BR0 = 2;            // (8MHz)/2 = 4MHz
    UCA1BR1 = 0;
    UCA1CTL0 |= UCCKPH + UCMST + UCSYNC;// Clock phase 0, Clock pol 0, 8-bit

    UCA1CTL1 &= ~UCSWRST;
}

  • 0
    Guru 227245 points

    For SPI usage, you don't need P5IN, P5OUT, P5DIR and P5REN. You only need P5SEL (and P3SEL), the rest is done by the USCI, including direction.

    When working with bits, you should use the binary operator '|' instead of the arithmetical operator '+'. While the result is the same in most cases, it may go epically wrong when the list of combined bits is not 'clean' (e.g. duplicate bits are set).
    You already correctly use '|=' and not '+='.

    Where/how do you measure the SPI clock speed? On P3.6? It should be the divided SMCLK, but only applies if something is actually sent.

    Do you see any change if you change UCA1BR0 to, say, 10 or more?

    Basically, your USCI setup seems okay. How do you configure your clock system?

  • 0 in reply to Jens-Michael Gross
    Prodigy 30 points

    Thank you Jens-Michael Gross for your reply,

    My clock configuration:

    // ACLK = XT1CLK = XT1LF (32kHz)
    // MCLK = DCODIV (8MHz)
    // SMCLK = DCODIV (8MHz)
    void InitializeClocks(void) {
        SetVCore(PMMCOREV_1);                     // Set VCore = 1.6V for 8MHz clock
        P7SEL |= BIT0 + BIT1;                     // Select XT1
        P5SEL |= BIT2 + BIT3;                        // Select XT2
        UCSCTL6 &= ~(XT1OFF + XT2OFF);            // XT1 On, XT2 On
        UCSCTL6 |= XCAP_3;                        // Internal load cap

        __bis_SR_register(SCG0);
        // Disable the FLL control loop
        UCSCTL0 = 0x0000;                          // Set DCOx = 31, MODx = 0
        UCSCTL1 = DCORSEL_7;                     // Select DCO range 16MHz operation
        UCSCTL2 = FLLD_1 + 243;                   // Set DCO Multiplier for 12MHz
                                                  // (N + 1) * FLLRef = Fdco
                                                  // (243 + 1) * 32768 = 8MHz
                                                  // Set FLL Div = fDCOCLK/2
        __bic_SR_register(SCG0);
        // Enable the FLL control loop

        // Worst-case settling time for the DCO when the DCO range bits have been
        // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
        // UG for optimization.
        // 32 x 32 x 12 MHz / 32,768 Hz = 375000 = MCLK cycles for DCO to settle
        __delay_cycles(250000);

        // Loop until XT1,XT2 & DCO fault flag is cleared
        do {
            UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
            // Clear XT2,XT1,DCO fault flags
            SFRIFG1 &= ~OFIFG;                      // Clear fault flags
        } while (SFRIFG1 & OFIFG);                   // Test oscillator fault flag

        UCSCTL6 &= ~XT1DRIVE_3;        // Xtal is now stable, reduce drive strength
    }

    However, you said that the divider only applies if I send something, and there might be were my issue is becuse when i set the UCA1BR0 = 20; i dont see any changes on the clock (P3.6), its still running on 8MHz.

    I will try send something and see if it changes.

    Thank You!

  • 0 in reply to Rafid Karim
    Prodigy 30 points

    I found the solution to my problem, my SPI and clock configuration was OK. The problem was that the NFC shield that I was using had a TXB0104PWR (4-BIT BIDIRECTIONAL VOLTAGE-LEVEL TRANSLATOR) that didn’t receive power on VccA.

    Thank you Jens-Michael Gross for clarifying the SPI configuration!

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