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Universal Clock System MS430FP5659 question

Hi,

    I'm using MS430FP5659 and I need to set the next UCS:

Seting   UCS  gives:
     -   11MHz  DCOCLK from 32kHz XT1 
     -    MCLK and SMCLK use DCOCLK
      -   ACLK uses XT1, 32kHz

here is my code:

////////////////////////////////////////////////////////

int main()

{

     P1DIR |= BIT0;             // ACLK set out to pins
     P1SEL |= BIT0;                              
     P3DIR |= BIT4;             // SMCLK set out to pins
     P3SEL |= BIT4;
    
     while(BAKCTL & LOCKBAK)   // Unlock XT1 pins for operation
       BAKCTL &= ~(LOCKBAK);
    
     UCSCTL1 |= 0x00;

     UCSCTL1 = DCORSEL_4;

     UCSCTL2 = UCSCTL2_DEFAULT;

      UCSCTL3 = SELREF_0;

      UCSCTL4 = SELS_3 + SELM_3;

      UCSCTL6 = XT2OFF + XT1DRIVE_3;
   
    __delay_cycles(343000);
   
      /* ------------------------------------------------------------------ */
    // Loop until XT1,XT2 & DCO fault flag is cleared
    do
    {
      UCSCTL7 &= ~(XT2OFFG | XT1LFOFFG | DCOFFG);  // Clear XT2,XT1,DCO fault flags
      SFRIFG1 &= ~OFIFG;                            // Clear fault flags
    }
    while (SFRIFG1&OFIFG);    // Test oscillator fault flag 

while(1){}
  }

Is everything correct here to have approx .  11MHz  DCOCLK from 32kHz XT1 ,
    MCLK and SMCLK use DCOCLK and    ACLK uses XT1, 32kHz?

Before in 5437 I used    P7SEL |= 0x03 to set  port used by XT1 but now in 5659 I guess it's obsolete since XIN/XOUT are not connected to any Px port.

Am I right?

 

Thanks,

 

 

  • Andrey Kamchatnikov said:
         UCSCTL1 |= 0x00;

    What shall this do? setting all bits in UCSCTL1 that are set in 0x00 is a void operation. Maybe you meant UCSCTL1 = 0? Or maybe UCSCTL0=0 (set the DCO to lowest tap)?
    Or
    UCSCTL1 = (UCSCTL1 & ~DCORSEL_7)|DCORSEL_4; // clear the current RSEL bits and set DCORSEL_4
    (DCORSEL_5 is also possible)

    Andrey Kamchatnikov said:
    UCSCTL2 = UCSCTL2_DEFAULT;

    What is this? UCSCTL2_DEFAULT is no symbol I ever heard of. If it equals the default register value, then setting it is superfluous and won't result in 11MHz DCOCLK. If it is something else, then it does something unknown, and the result of the whole code is unknown.

    Andrey Kamchatnikov said:
        __delay_cycles(343000);

    Why do you wait here? The following loop will already wait until the crystal is ready. And before the crystal is ready, the FLL will adjust the DCO based on REFO, so after the crystal is running, you'll have to wait again (but not as much) anyway. Since you start with a slow MCLK, 343k cycles wait is quite long anyway. (the maximum adjustment time is 322k anyway, when not considering the slow MCLK start.)

    However, to run with 11MHz (>8MHz), you need PMMCOREVx>=1. If you push MCLK that high without changing the default core voltage setting, the CPU will likely crash.

  • Thank you for your respond:

    I modified so:

           set PMMCOREVx=1 

         1.   UCSCTL1 = 0x00;

          2. UCSCTL1 = DCORSEL_5;

          3. UCSCTL2 = FLLD_1 + 340; // 340*32768 = 11141120 Hz

         4.   UCSCTL3 = SELREF_0;

         5.  UCSCTL4 = SELS_3 + SELM_3;

         6.  UCSCTL6 = XT2OFF + XT1DRIVE_3;
       
       //checking loop
         do
        {
          UCSCTL7 &= ~(XT2OFFG | XT1LFOFFG | DCOFFG); 
          SFRIFG1 &= ~OFIFG;                          
        }
        while (SFRIFG1&OFIFG);   


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