TimerA Setup Issue

Tom N said:

1. Do I need to setup TACCTL0 for this to work properly?

No. The value in TACCR0 is active for up or up/down mode even if TACCTL0 is in default configuration (inactive).

Tom N said:

2. If I toggle the TACLR pin, does it only reset the counters, or does it reset or latch in the set up data as well?

Pin? Bit! :)
It clears the TAR register. It also clears teh prescalers, but sicne these are down counters, clearing them means the timer will count on the next clock pulse independent of the divider. But your dividers are set to /1 anyway.

Tom N said:

Is there a state diagram anywhere of the steps to setup the TimerA compare mode for PWM signals?

No, the timers aren't as complex as the ADC or the USCI. The whole functionality can be described by a (relatively) simple logic diagram. The only 'order' that needs to be taken into account is the clock timing. Especially if the timer clock is asynchronous to MCLK, so reads may happen while TAR is in the process of counting.

Tom N said:

OUTMODx=110 Toggle/Set CCIE=0 Int Disabled, CCI=0, OUT=1

Hmmm, OUT=1 is irrelevant, as you at the same time switch to a different mode than OUTMOD_0. So TA1 starts low. (the OUT bit does NOT reflect the current output state. it is only changed by software and only affect soutput in OUTMOD_0)

Tom N said:

Instead I get a clock that is high for 200 and low for 200 on TA0.

Sure you configure TACCTL1 and not TACCTL0? 200/200 is what I would expect if TACCTL0 would run in TOGGLE mode and TACCR0 set to 100 (not TACCR1).
TACCTL1, if untouched, would show a plain low. So check your register addresses. :)

Tom N said:

I expect to get a 33% duty cycle clock since TACCR0 = 150 and TACCR1=100 (100 TACLK cycles low then 100 TACLK cycles high, then 200 TACLK cycles low, then 100 high, then 200 low...)

Well, not if you use toggle/set mode. Assume you start low (which you do, even though you set OUT to 1 - see my previous post).

On 100 it will toggle high, on 150 it will stay high, back on 100, it will toggle low, on 0 it will set high, on 100 toggle low, on 150 stay low, on 100 toggle high, on 0 stay high, and so on. So you'll get 100 low and 200 high after an initial 100-100-100 cycle.

Jens-Michael Gross said:

]Sure you configure TACCTL1 and not TACCTL0? 200/200 is what I would expect if TACCTL0 would run in TOGGLE mode and TACCR0 set to 100 (not TACCR1).

TACCTL1, if untouched, would show a plain low. So check your register addresses. :)

I think this may be an indicator of my issue.  According to the documentation, I am programming the correct addresses.  Also, I initially set up the OUT bit in OUT mode and toggle each port once to verify that it is working and it is.

Timer_A control                   TACTL       0160h
Timer_A counter                   TAR         0170h
Timer_A capture/compare control 0 TACCTL0     0162h
Timer_A capture/compare 0         TACCR0      0172h
Timer_A capture/compare control 1 TACCTL1     0164h
Timer_A capture/compare 1         TACCR1      0174h
Timer_A capture/compare control 2 TACCTL2     0166h
Timer_A capture/compare 2         TACCR2      0176h
Timer_A interrupt vector          TAIV        012Eh 

Here is my latest attempt:

IR_SHIFT("IR_CNTRL_SIG_16BIT")
DR_SHIFT16(0x2408) : Set to Write
IR_SHIFT("IR_ADDR_16BIT")
DR_SHIFT16(0x0172) : Set Timer_A capture/compare 0 TACCR0 Register Address
IR_SHIFT("IR_DATA_TO_ADDR") : Stop the timer
DR_SHIFT16(0x0000) : Write to TACCR0 Control Register 000 = 0x0000
SetTCLK
ClrTCLK
IR_SHIFT("IR_CNTRL_SIG_16BIT")
DR_SHIFT16(0x2408) : Set to Write
IR_SHIFT("IR_ADDR_16BIT")
DR_SHIFT16(0x0160) : Set Timer_A control TACTL Register Address
IR_SHIFT("IR_DATA_TO_ADDR") : Clear and reset timer
DR_SHIFT16(0x0004) : Write to TACTL Control Register TASSELx=00 TACLK, IDx=00 /1, MCx=00 Stop, TACLR = 1, TAIE interrupt disable 0, TAIFG interrupt flag 0  0000 0000 0000 0100
SetTCLK
ClrTCLK
IR_SHIFT("IR_CNTRL_SIG_16BIT")
DR_SHIFT16(0x2408) : Set to Write
IR_SHIFT("IR_ADDR_16BIT")
DR_SHIFT16(0x0172) : Set Timer_A capture/compare 0 TACCR0 Register Address
IR_SHIFT("IR_DATA_TO_ADDR")
DR_SHIFT16(0x0096) : Write to TACCR0 Control Register 150 = 0x0096
SetTCLK
ClrTCLK
IR_SHIFT("IR_CNTRL_SIG_16BIT")
DR_SHIFT16(0x2408) : Set to Write
IR_SHIFT("IR_ADDR_16BIT")
DR_SHIFT16(0x0174) : Set Timer_A capture/compare 1 TACCR1 Register Address
IR_SHIFT("IR_DATA_TO_ADDR")
DR_SHIFT16(0x0064) : Write to TACCR1 Control Register 100 = 0x0064
SetTCLK
ClrTCLK
IR_SHIFT("IR_CNTRL_SIG_16BIT")
DR_SHIFT16(0x2408) : Set to Write
IR_SHIFT("IR_ADDR_16BIT")
DR_SHIFT16(0x0164) : Set Timer_A capture/compare control 1 TACCTL1 Register Address
IR_SHIFT("IR_DATA_TO_ADDR")
DR_SHIFT16(0x00C4) : Write to TACCTL1 Control Register CMx=00 No cap, CCISx=00, SCS=0, SCCI=0, CAP=0 Compare, OUTMODx=110 Toggle/Set CCIE=0 Int Disabled, CCI=0, OUT=1, COV=0, CCFIG=0 0000 0000 1100 0100
SetTCLK
ClrTCLK
IR_SHIFT("IR_CNTRL_SIG_16BIT")
DR_SHIFT16(0x2408) : Set to Write
IR_SHIFT("IR_ADDR_16BIT")
DR_SHIFT16(0x0160) : Set Timer_A control TACTL Register Address
IR_SHIFT("IR_DATA_TO_ADDR")  : OUT0 should be toggle with a 50% duty cycle at 1/100 * input clock
DR_SHIFT16(0x0030) : Write to TACTL Control Register TASSELx=00 TACLK, IDx=00 /1, MCx=11 Updown Mode, TACLR = 0, TAIE interrupt disable 0, TAIFG interrupt flag 0  0000 0000 0011 0000
SetTCLK
ClrTCLK