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Single Master and Multiple SPI Slaves

Prad1
Genius 3825 points

Hi,

We need some advice about connecting Multiple(upto 8) salves in SPI communication.
In our application we need to communicate between one TIVA C(Master) and 8 MSP430(slaves).

Please let me know which is the better solution to control MSP430(slaves),
currently we are trying to synchronize the slaves through GPIO interrupt,
but as the slaves should be running all time(without reset),we are not able to
synchronize the slaves just with a GPIO interrupt.

It would be helpful if there is any reference on how to control multiple
MSP430 slaves without resetting it to synchronize.

Regards
prad.

  • 0
    Guru 46710 points

    Prad1 said:
    we are not able to synchronize the slaves just with a GPIO interrupt.

    It is not clear what exactly you can't achieve. Please explain in details.

  • 0
    Guru 227245 points

    In SPI, data transfer is synchronized by the master by asserting a dedicated chip select line for each slave. If the line is low, the slave is selected and responds to the bus, if it is high, the slave is deaf and silent.
    The chip select is controlled by software, any normal GPIO pin can be used. The SPI hardware does not know which slave is selected. It only sends and receives bits.

    On the slave side, the 4-pin SPI mode can be used. The STE pin will control bus clock reception and data output enable of the slave. However, the chip select must still be checked and acted on by software. STE is only to keep the bus free and does not manage internal protocol issues. (e.g. on chip select, a new byte transfer starts. Also, maybe the high-level multi-byte protocol is reset or not -  it depends on software convention and is not part of SPI specs). STE only 'gates' the SOMI and SCL pins. Applying a reset to the hardware after CS is de.-asserted is left to the software.

    This only applies to MSPs with USCI module. On MSPs with USI module, things are (a bit) different (e.g. there is no 4-pin mode)

  • 0 in reply to Jens-Michael Gross
    Guru 46710 points

    Jens-Michael Gross said:
    This only applies to MSPs with USCI module. On MSPs with USI module, things are (a bit) different (e.g. there is no 4-pin mode)

    Things are different but not difficult. Especially if both - master and all the slaves are under your control. Every SPI slave have it's reaction time to CS which shall be obeyed by master. If your slaves are slow - then master shall delay transfer after asserting CS of particular slave.

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