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Efficient RF Register Setup for CC430



I've noticed that most source code examples for the CC430 set up the RF registers with something like this:

/*================================ WriteRfSettings =================================
** @fn WriteRfSettings
** @brief Write the minimum set of RF configuration register settings
** @param RF_SETTINGS *pRfSettings Pointer to the structure that holds the rf settings
** @return none
**--------------------------------------------------------------------------------*/
void WriteRfSettings(RF_SETTINGS *pRfSettings)
{
WriteSingleReg(SYNC1, pRfSettings->sync1);
WriteSingleReg(SYNC0, pRfSettings->sync0);
WriteSingleReg(FSCTRL1, pRfSettings->fsctrl1);
.....

}

This calls WriteSingleReg for each register and value. As far as I can tell, this takes up over 800 bytes of code space just to initialize the RF registers. Wouldn't it be more efficient to set up the RfSettings structure so that the ordering matched the RF registers, and just make a single call to WriteBurstReg to initialize these? Or is there some reason why this wouldn't work? 

I haven't actually tried this yet, but I'm looking for ways to reduce my overall code size, and this seemed like a big one...

  • Usually samples are made to easy understand and to easy play with them, modify. Code and performance efficiency is last priority for examples if they are not about code or performance efficiency. I doubt radio samples are. Of course you can optimize sample code - especially if you don't change register init sequence and delays, if any.

  • This may not seem like a surprise to most people, but I gave it a try and was able to save 900 bytes compared to the TI sample function.

    Here's a copy of the shorter version of this in case someone wants to save some code space; although I'm guessing most people have already done something similar. The following writes the RF register values starting with FIFOTHR and ending with FSCAL0:

    void WriteRfSettings (void)
    {
    unsigned char rfSettingsBuffer[36] =
    {
    0x0E, // FIFOTHR RXFIFO and TXFIFO thresholds.
    0xB4, // SYNC1
    0x4A, // SYNC0
    0x78, // PKTLEN Packet length.
    0x64, // PKTCTRL1 Packet automation control. MAKE SURE PQT is enabled!!!
    0x45, // PKTCTRL0 Packet automation control. Data whitening on, CRC Enabled, variable packet length
    0x00, // ADDR Device address.
    0x01, // CHANNR Channel number.
    0x0C, // FSCTRL1 Frequency synthesizer control.
    0x00, // FSCTRL0 Frequency synthesizer control.
    0x22, // FREQ2 Frequency control word, high byte.
    0xB1, // FREQ1 Frequency control word, middle byte.
    0x9F, // FREQ0 Frequency control word, low byte. 902Mhz.
    0x28, // MDMCFG4 Modem configuration.
    0x93, // MDMCFG3 Modem configuration. Datarate = 38383.5Hz
    0x03, // MDMCFG2 Modem configuration. DC Blocking on, 2-FSK, No Manchester encoding, 30/32 sync bit
    0x22, // MDMCFG1 Modem configuration.
    0xF8, // MDMCFG0 Modem configuration. 199.951Khz Channel Spacing
    0x66, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
    0x17, // MCSM2
    0x00, // MCSM1 Main Radio Control State Machine configuration.
    0x00, // MCSM0 Main Radio Control State Machine configuration.
    0x3F, // FOCCFG Frequency Offset Compensation Configuration.
    0x1D, // BSCFG Bit synchronization Configuration.
    0x07, // AGCCTRL2 AGC control.
    0x0C, // AGCCTRL1 AGC control.
    0xB0, // AGCCTRL0 AGC control.
    0x80, // WOREVT1
    0x00, // WOREVT0
    0xF0, // WORCTRL
    0xB6, // FREND1 Front end RX configuration.
    0x10, // FREND0 Front end TX configuration.
    0xE9, // FSCAL3 Frequency synthesizer calibration.
    0x2A, // FSCAL2 Frequency synthesizer calibration.
    0x00, // FSCAL1 Frequency synthesizer calibration.
    0x1F, // FSCAL0 Frequency synthesizer calibration.
    };

    WriteBurstReg (FIFOTHR, &rfSettingsBuffer[0], 36); ///// Change #69

    }

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