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MSP430F5308 XT1 not running

Gary Richardson
Intellectual 400 points
Other Parts Discussed in Thread: MSP430F5308

Below is some code for an MSP430F5308 that outputs ACLK on P1.0.
When run though, the frequency of the output on P1.0 is 32.9 KHz
The signal at XIN (P5.4) has frequency of 32768 Hz.
The signal on P1.1 has a frequency of 75.2 KHz.
The XT1LFOFFG bit of USCTL7 is set indicating that an XT1 fault condition
exists. What is wrong with this code?

#include "io430.h"
int main (void)
{
    WDTCTL = WDTPW + WDTHOLD;       // Stop watchdog timer
    P1DIR = P4DIR = 0xFF;           // Set all ports to output
    P2DIR = 1;
    P5DIR = 0x3F;
    P6DIR = 0xF;
    P1OUT = P2OUT = P4OUT = P3OUT = P6OUT = 0;

    P5DIR &= ~BIT4;          // XIN an input
    P5SEL |= BIT4|BIT5;     // Enable XT1
    UCSCTL6 &= ~XT1OFF_L;   // XT1 on
    P1SEL |= BIT0;          // Enable ACLK output on P1.0
    while (1)
        P1OUT ^= BIT1;
}

  • 0
    Guru 227245 points

    After start, XT1 is not running. So any clock driven by XT1 will use its fallback. ACLK will be driven by REFO in this case.

    Even if the crystal is finally running (which can take several 100 ms up to seconds), ACLK wills till run from the fallback. You'll have to wait until you can clear the clock fault flags. Only if OFIFG is clear (which requires all oscillator fault flags to be clear) the clock system will switch ACLK to the desired XT1 input.

    Gary Richardson said:
    When run though, the frequency of the output on P1.0 is 32.9 KHz

    That's your REFO clock speed. 32768Hz +-1.5%

    Gary Richardson said:
    The signal at XIN (P5.4) has frequency of 32768 Hz.

    How did you measure that? Any normal scope probe on the crystal will add so much capacitance that it will totally detune the crystal at best (and stop oscillation at worst). We use an active FET probe (0.9pF input capacitance, ~$700) for this, but most people likely don't have one.

    Gary Richardson said:
    The signal on P1.1 has a frequency of 75.2 KHz.

    MCLK runs from DCO. The DCO should be adjusted by the FLL to 2MHz by default - after some time (and the CPU running on DCOCLK/2 by default). Execution of the code takes 4 cock cycles for the toggle, and two for the jump, so a complete output cycle takes 12 MCLK cycles. Apparently, your DCO runs on 1.8MHz then, and the CPU therefore on 900kHz.

  • 0
    Intellectual 400 points

    Jens-Michael,

    I finally realized what was going on and changed the while loop in my code to:

        while (1)
        {
            if (UCSCTL7 & XT1LFOFFG)
            {
                UCSCTL7 &= ~XT1LFOFFG;
                SFRIFG1 &= ~OFIFG;      // Clear LFXT1 fault
                P1OUT ^= BIT1;
            }
            else
                P1OUT ^= BIT2;
        }

    I now see the 32867 Hz signal on P1.0. By looking at P1.1 I see that the crystal fault condition persists for a little over 300 ms.

    I measured the crystal frequency at P5.4 by with my Tek TDS 1012 oscilloscope using an ordinary probe. 

    Also, the while loop of the original code required 7 cycles (compiled with IAR) so the 75.2 KHz signal implys a clock frequency of 1.05 MHz which is close to the 1.048 MHz expected.

    Many thanks for your reply to my post.

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