PLZ Handling ADC sampling rate & UART transmit speed for waveform

Junwoo Yoo

I'd like to make a PPG&GSR signal waveform mornitoring system by MSP430&Android.

My system is simply ADC12(12bit) -> NumToString(for 1signal(2chanel)12Char=12byte=96bit) -> UART(8bit, 119200bps) -> Bluetooth(8bit, 1~3MB/s) -> Android

But I just get 50~60sample per second(I need 200~300sample per second). I guess my problem is in Timer or Main Clock or UART.

My question is...

1. When I changed Timer clock register(TA1CCR0), nothing changed(I still got same sample per second)

2. My freind uses NumToBinary algorithm and get around 250 sample per sec, I know it is more effiecient than my way. But I don't know why even I chaned up UART speed it doesnt works. I messured this. UART speed is 119200bps=14.4kB/s and 1 signal(12char=12byte). So, 14400/12=1200 sample per sec. am I wrong?

I don't know exactly know what is the problem and looking forward to your help

thanks indeed.

I attach my main code

----------------------------------

void main(void) {

WDTCTL = WDTPW + WDTHOLD; // Stop watch dog timer

//Initialize LCD

halLcdInit();

halLcdBackLightInit();

halLcdSetBackLight(0);

halLcdSetContrast(100);

halLcdClearScreen();

__bis_SR_register(SCG0); // Disable the FLL control loop

UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx

UCSCTL1 = DCORSEL_7; // Select DCO range 16MHz operation

UCSCTL2 = FLLD_1 + 249; // Set DCO Multiplier for 8MHz

// (N + 1) * FLLRef = Fdco

// (249 + 1) * 32768 = 8MHz

// Set FLL Div = fDCOCLK/2

__bic_SR_register(SCG0); // Enable the FLL control loop

//Initialize ADC12_A

P7SEL |= 0x50; // Enable A/D channel Port7.4, 7.6 (A12, A14)

ADC12CTL0 = ADC12ON+ADC12MSC+ADC12SHT1_0;// Turn on ADC12, set sampling time , ADC12CLK Cycle 4

ADC12CTL1 = ADC12SHP+ADC12CONSEQ_3+ADC12DIV_0; // Use sampling timer, Repeat-sequence-of-channels

//ADC12CTL2 = ADC12RES_3;

ADC12MCTL9 = ADC12INCH_12;// ref+=AVcc, channel = A12, ADC_12A Memory Control 9

ADC12MCTL11 = ADC12INCH_14+ADC12EOS;// ref+=AVcc, channel = A14, ADC_12A Memory Control 11

ADC12IE = 0xF080; //Enable ADC12IFG7, ADC12IFG15

ADC12CTL0 |= ADC12ENC; // Enable conversions

//Initialize UART

P3SEL = 0x30; //Port3.4, 3.5

UCA0CTL1 |= UCSWRST; // **Put state machine in reset**

UCA0CTL1 |= UCSSEL_2; // CLK = SMCLK 8Mhz

UCA0BR0 = 4; // 8MHz/9600=69.44 (see User's Guide)

UCA0BR1 = 0x00; // 32.3.13 Typical Baud Rates and Errors

UCA0MCTL = UCBRS_5+UCBRF_3+UCOS16; // Modulation UCBRSx=5, UCBRFx=3, Oversamping ON

UCA0CTL1 &= ~UCSWRST;

UCA1IE |= UCRXIE;

//Initialize Timer

TA1CCTL0 = CCIE; // CCR0 interrupt enabled

TA1CCR0 = 8333; // 8MHz/8333ms divide =

TA1CTL = TASSEL_2 + MC_1; // SMCLK 1MHz, Continuous mode, clear TAR

__enable_interrupt();

while(1);

}

// Timer A0 interrupt service routine

#pragma vector=TIMER1_A0_VECTOR

__interrupt void TIMER1_A(void)

{

while(1){

ADC12CTL0 |= ADC12SC; // Start conversion

__bis_SR_register(LPM0_bits+GIE);

}

// ADC12 interrupt service routine

#pragma vector=ADC12_VECTOR

__interrupt void ADC12_ISR(void){

readADC();

}

void readADC(){

sum_data[0] = (unsigned int)ADC12MEM9; // Move sum_data[0], IFG is cleared p.7.4

sum_data[1] = (unsigned int)ADC12MEM11; // Move sum_data[1], IFG is cleared p.7.5

numtostring(sum_data[0],sum_data[1]);

}

void numtostring(long num, long num2){

char str[12] = {' '};

int tmp;

int i = 0;

int j,k,l;

while(num!=0){

for(j=i; j>0; j--){

*(str+j) = *(str+j-1);

}

tmp = num%10;

if(tmp==0)

*str='0';

else if(tmp==1)

*str='1';

else if(tmp==2)

*str='2';

else if(tmp==3)

*str='3';

else if(tmp==4)

*str='4';

else if(tmp==5)

*str='5';

else if(tmp==6)

*str='6';

else if(tmp==7)

*str='7';

else if(tmp==8)

*str='8';

else if(tmp==9)

*str='9';

num = num / 10;

i++;

}

str[i++]='A';

str[i++]='/';

k=i;

halLcdPrintLineCol("PPG", 3, 1, OVERWRITE_TEXT);

halLcdPrintLineCol(str, 3, 7, OVERWRITE_TEXT);

while(num2!=0){

for(j=i; j>k; j--){

*(str+j) = *(str+j-1);

}

tmp = num2%10;

if(tmp==0)

*(str+k)='0';

else if(tmp==1)

*(str+k)='1';

else if(tmp==2)

*(str+k)='2';

else if(tmp==3)

*(str+k)='3';

else if(tmp==4)

*(str+k)='4';

else if(tmp==5)

*(str+k)='5';

else if(tmp==6)

*(str+k)='6';

else if(tmp==7)

*(str+k)='7';

else if(tmp==8)

*(str+k)='8';

else if(tmp==9)

*(str+k)='9';

num2 = num2 / 10;

i++;

}

str[i++]='B';

str[i++]='/';

halLcdPrintLineCol("GSR", 5, 1, OVERWRITE_TEXT);

halLcdPrintLineCol(str+k, 5, 7, OVERWRITE_TEXT);

for(j=0;j<i; j++){

while (!(UCA0IFG&UCTXIFG)); // USCI_A0 TX buffer ready?

UCA0TXBUF = str[j];

}

over 12 years ago

0 Jens-Michael Gross over 12 years ago

Guru 227245 points

Junwoo Yoo said:
TA1CTL = TASSEL_2 + MC_1; // SMCLK 1MHz, Continuous mode, clear TAR

MC_1 is up mode, but that's okay, I guess.
In continuous mode, the timer runs from 0 to 65535. Changes in CCR0 change the moment at which CCR0-IRQ is triggered, but not the frequency. In Up mode, however, the timer counts from 0 to CCR0, so changing CCR0 changes the trigger frequency.

Junwoo Yoo said:
TA1CCR0 = 8333; // 8MHz/8333ms divide =

It's actually /8334 then, as '0' is a count too. However, this should result in 1.04ms interrupt frequency.

Junwoo Yoo said:
#pragma vector=TIMER1_A0_VECTOR
__interrupt void TIMER1_A(void)
{
   while(1){
      ADC12CTL0 |= ADC12SC; // Start conversion
      __bis_SR_register(LPM0_bits+GIE);
   }
}

First, you can trigger the ADC directly by a timer output (use the proper OUTMOD setting). Check your device datasheet to see which timer output can be used to directly trigger the ADC. You don't need an ISR then at all.

Then, you enter LPM inside an ISR. That's a death sin. It means your ISR will not exit, but will be interrupted by another ISR then. Worst case, this will fill your stack so it overflows, overwriting your variables first, then flushing into the void, crashing the CPU.

If you want the system to return to LPM where it was before, you can simply exit the ISR, This will restore the previous LPM state.
If you want to change the LPM state after the ISR exits (!) Use the __bis_SR_register_on_exit() intrinsic (or __bic...) instead (there are multiple different aliases of this intrinsic, check your compiler documentation.

Another thing: in sequence or repeated modes, ADC12SC needs to be cleared before it can be set again. The trigger is edge-sensitive. Only in single conversion mode, ADC12SC clears when the conversion is done.

However, you're setting ADC12SHP and MSC bits. This means, once started, the ADC will run the sequence over and over again with fastest speed, until you clear the ENC bit. This is why your timer has no effect at all, and changes on CCR0 won't change anything. Clear the MSC bit if you want to trigger each single conversion of the sequence separately. Or use sequence mode (instead of repeated sequence mode). In this case, your timer ISR can trigger the conversion of a new sequence by clearing and then setting the ADC12SC bit.

Junwoo Yoo said:
__enable_interrupt();
while(1);

Why don't you enter LPM right here and leave it this way?

while(1) __bis_SR_register(LPM0_bits | GIE);

Junwoo Yoo said:
__interrupt void ADC12_ISR(void){
readADC();
}

That's a bad idea. Calling functions from inside an ISR should be avoided.
The function call forces the compiler to assume that the parameter passing registers are clobbered during the function call (standard calling convention). So it has to save them on stack. Simply move the function content directly into the ISR instead of making it a function. Otherwise you're wasting time and space. And ISRs should be as fast as possible.

Also, your function called inside the ISR does so some really time-consuming things, like LCD output. This is misplaced in an ISR execution. The ISR should simply collect the data and then wake main, telling it (implicitly because of the wake, or explicitly by a global flag) that new data needs to be processed and sent.

ISRs are no threads. ISRs are fast-in, fast out handlers for events. They shouldn't do more than immediately necessary to handle the event. Everything else should be done in main.

So teh ADC ISR copies the data from ADC12MEM, clearing the IFG bits, then calls __bic_SR_register_on_exit(LPM0_bits).
In main, you do

while(1) {
__bis_SR_register(LPM0_bits | GIE);
_no_operation(); // don't put a breakpoint here right after entering LPM
// new data has been arrived
// process and display it
// then loop back into LPM
}

0 Junwoo Yoo over 12 years ago in reply to Jens-Michael Gross

Prodigy 130 points

Jens-Michael Gross said:

First, you can trigger the ADC directly by a timer output (use the proper OUTMOD setting). Check your device datasheet to see which timer output can be used to directly trigger the ADC. You don't need an ISR then at all.

1. Acording to datasheets about OUTMOD..

Could you let me know which is for my system? I don't understand this register...

-------------------------------------

17.2.5.1 Output Modes

The output modes are defined by the OUTMOD bits and are described in Table 17-2. The OUTn signal is

changed with the rising edge of the timer clock for all modes except mode 0. Output modes 2, 3, 6, and 7

are not useful for output unit 0 because EQUn = EQU0.

Table 17-2. Output Modes

OUTMODx Mode Description

000 Output The output signal OUTn is defined by the OUT bit. The OUTn signal updates immediately when OUT is updated.

001 Set The output is set when the timer counts to the TAxCCRn value. It remains set until a reset of the timer, or until another output mode is selected and affects the output.

010 Toggle/Reset The output is toggled when the timer counts to the TAxCCRn value. It is reset when the timer counts to the TAxCCR0 value.

011 Set/Reset The output is set when the timer counts to the TAxCCRn value. It is reset when the timer counts to the TAxCCR0 value.

100 Toggle The output is toggled when the timer counts to the TAxCCRn value. The output period is double the timer period.

101 Reset The output is reset when the timer counts to the TAxCCRn value. It remains reset until another output mode is selected and affects the output.

110 Toggle/Set The output is toggled when the timer counts to the TAxCCRn value. It is set when the timer counts to the TAxCCR0 value.

111 Reset/Set The output is reset when the timer counts to the TAxCCRn value. It is set when the timer counts to the TAxCCR0 value

The output modes are defined by the OUTMOD bits and are described in Table 17-2. The OUTn signal is

changed with the rising edge of the timer clock for all modes except mode 0. Output modes 2, 3, 6, and 7

are not useful for output unit 0 because EQUn = EQU0.

Table 17-2. Output Modes