Other Parts Discussed in Thread: MSP430F5325
Dear All,
For MSP430F5325 we used the crystal oscillator 32768Hz in low frequency mode (XT1) and DVCC
of 3.3V. Using 32768Hz crystal we are able to generate SMCLK from FLL upto 18 Mhz but when we try to go for the higher frequencies that is 20 Mhz/25 Mhz are not working .
kindly refer the below code for your reference ,kindly note commented part is for 18 Mhz which is working fine ,we have a problem for 20Mhz and higher frequencies.
Kindly help to resolved the problem.
//////////////////////Defination
// For 18 Mhz
/* # define DCO_RANGE DCORSEL_7 //DCORSEL_7 for 16.77 MHZ
# define DCO_MULTIPLIER 551 //551 for 18.055 MHZ
*/
// for 20 Mhz
# define DCO_RANGE DCORSEL_4 //DCORSEL_4 for 20.021 MHZ
# define DCO_MULTIPLIER 611 //611 for 20.021 MHZ
///////////////////////////////////////// DC0 stabilization start
P5SEL |= BIT4+BIT5; // Select XT1
UCSCTL6 |= BIT7+BIT6; // Reduce XT1 DRIVE STRENGTH
UCSCTL6 &= ~BIT5; // XT1 mode select ,XTS=0
UCSCTL6 &=~BIT4; //
UCSCTL6 &= ~(XT1OFF); // XT1 On
UCSCTL6 |= XCAP_3; // Internal load cap
UCSCTL3 = 0; // FLL Reference Clock = XT1
// Loop until XT1,XT2 & DCO stabilizes - In this case loop until XT1 and DCo settle
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG); // Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
} while (SFRIFG1&OFIFG); // Test oscillator fault flag
UCSCTL6 &= ~(XT1DRIVE_3); // Xtal is now stable, reduce drive strength
UCSCTL4 |= SELA_0; // ACLK = LFXT1 (by default)
////////////////////////////////////Start of DCo 20Mhz (locked to 32Khz by FLL/////////////////////////////
//UCSCTL3 = SELREF_0; // Set DCO FLL reference = XT1CLK (external watch 32kHz)
UCSCTL4 |= SELA_0; // Set ACLK = XT1CLK (external watch 32kHz)
__bis_SR_register(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
////////////////////////////////////////////////// ///////////////////////// 18MHz
/* UCSCTL1 = DCO_RANGE; //DCORSEL_7;
UCSCTL2 = FLLD_1 + DCO_MULTIPLIER; // 551; //18055168Hz
*/
///////////////////////////////////////////////////// 20 Mhz
UCSCTL1 = DCO_RANGE; //DCORSEL_4;
UCSCTL2 = FLLD_1 + DCO_MULTIPLIER; //611 // 20021248
__bic_SR_register(SCG0); // Enable the FLL control loop
// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
// 32 x 32 x 8 MHz / 32,768 Hz = 250000 = MCLK cycles for DCO to settle
__delay_cycles(250000);
// Loop until XT1,XT2 & DCO stabilizes - In this case only DCO has to stabilize
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
} while (SFRIFG1&OFIFG); // Test oscillator fault flag
/////////////////////////////////End of DCO stabilization/////////////////////
