Minimum time needed for the ADC conversion

Govardhan Reddy Patancheru

Hi,

I am planning to use a sampling rate of 100Hz meaning that each sample will be collected in 10ms using the timer and by suing the 32KHz ACLK.can someone explain what should be the minimum and maximum time needed for the ADC12 sample conversion.

what factors will effect the ADC12 conversion time calculation and how the selected(min and max) time will effect the conversion result.

thankyou.

over 11 years ago

0 Ilmars over 11 years ago

Guru 46710 points

Govardhan Reddy Patancheru said:
can someone explain what should be the minimum and maximum time needed for the ADC12 sample conversion.

User's Guide usually have answers to such kind of questions. You shall check your chip datasheet, ADC clock frequency range, then check User's Guide about ADC sampling and conversions time which usually is specified in ADC clock periods.

For 100Hz sampling rate you can't run ADC continuously but shall run sampling timer starting conversions at 100Hz instead

0 Govardhan Reddy Patancheru over 11 years ago in reply to Ilmars

Intellectual 840 points

Thanks,

I was able to make this for the sampling rate of 100Hz with the timer uisng 32Khz clk and each ADc conversion will finish in 0.5 sec .

void main void()
{
	REFCTL0 = REFMSTR + REFON;
	ADC12CTL0 = ADC12SHT0_1 + ADC12REFON + ADC12REF2_5V+ADC12ON;
	ADC12CTL1 = ADC12SHS_1 + ADC12SHP ;
	ADC12CTL2 = ADC12PDIV + ADC12RES_2;
	ADC12MCTL0 = ADC12SREF_1 + ADC12INCH_4;
	P2SEL = BIT4;
	ADC12IE = ADC12IE0;
	ADC12CTL0 |= ADC12ENC;
	TA0CCR0 = ACLK/(100) - 1;
	TA0CCR1 = TA0CCR0 - 20;
	TA0CCTL1 = OUTMOD_3;
	TA0CTL = TASSEL_1 + MC_1;
	while (1)
	{
		ADC12CTL0 |= ADC12SC;
		__bis_SR_register(CPUOFF + GIE);
	}
}
#pragma vector=ADC12_VECTOR
__interrupt void ADC12ISR(void)
{
    result=ADC12MEM0;
    __bic_SR_register_on_exit(CPUOFF);
}

Things needed for ADC clock cycles

frequency =32khz/(17)=1888Hz
time needed=0.5ms
timer is running at 100Hz=10ms

but I got these doubts

1)TA0CCR0=320-1=319
TA0CCR1=299
what should be the minimum difference(gap) needed between TA0CCR0 and TA0CCR1 to get the required ADC conversion time and sampling rate.

2)Is this the correct way to calculate ADC conversion time (needed) and sampling rate or will there be any problem.

Thankyou.

0 Jens-Michael Gross over 11 years ago in reply to Govardhan Reddy Patancheru

Guru 227245 points

The sampling rate (the time at which a new conversion is started) only depends on the timer cycle time, defined by CCR0.

If using the ADCs internal sample timing (ADC12SHP=1 and ADC12SHTx set properly), then the minimum pulse required to trigger a conversion is 1 ASC12CLK cycle. (maybe even less, but I'm not sure)

If not setting ADC12SHP, ADC12SHTx is void and the delay between CCR1 and CCR2 defines the charge time for the sampling capacitor, followed by 13 ADC12CLk cycles for the conversion.

However, check the datasheet and the errata sheet. There's a minimum ADC12CLK frequency of ~400kHz. So clocking the ADC12 with 32768Hz (as your calculation seems to indicate) won't work. But you don't set ACLK for the ADC12 a clock source anyway, so the ADC12 runs on default 6MHz/4 = 1.5MHz.

With 21 cycles (ADC12SHT_1 = 8, +13 for conversion), this means 14µs conversion time. (maximum 71ksps). Not 0.5ms.

Also, ACLK is likely 32768Hz, not 32000Hz, so CCR0 should be 327, not 319.

0 old_cow_yellow over 11 years ago in reply to Govardhan Reddy Patancheru

Guru 58965 points

Govardhan Reddy Patancheru said:

void main void()
{
	REFCTL0 = REFMSTR + REFON;
	ADC12CTL0 = ADC12SHT0_1 + ADC12REFON + ADC12REF2_5V+ADC12ON;
	ADC12CTL1 = ADC12SHS_1 + ADC12SHP ;
	ADC12CTL2 = ADC12PDIV + ADC12RES_2;
	ADC12MCTL0 = ADC12SREF_1 + ADC12INCH_4;
	P2SEL = BIT4;
	ADC12IE = ADC12IE0;
	ADC12CTL0 |= ADC12ENC;
	TA0CCR0 = ACLK/(100) - 1;
	TA0CCR1 = TA0CCR0 - 20;
	TA0CCTL1 = OUTMOD_3;
	TA0CTL = TASSEL_1 + MC_1;
	while (1)
	{
		ADC12CTL0 |= ADC12SC;
		__bis_SR_register(CPUOFF + GIE);
	}
}
#pragma vector=ADC12_VECTOR
__interrupt void ADC12ISR(void)
{
    result=ADC12MEM0;
    __bic_SR_register_on_exit(CPUOFF);
}

If that is all the code there is, it will not work.

0 Govardhan Reddy Patancheru over 11 years ago in reply to old_cow_yellow

Intellectual 840 points

Hi again,

"Old_cow_yellow"-This is the original code

 #include <msp430.h>

#define Aclk 32768u//Auxiliary clock of 32768Hz
int result=0;

int _system_pre_init(void)
{
	WDTCTL = WDTPW | WDTHOLD;
	return(1);
}

void main( void )
{
  REFCTL0 =REFON;//for selecting 2.5V reference 
  ADC12CTL0 = ADC12SHT0_0 + ADC12REFON + ADC12REF2_5V+ADC12ON;
  ADC12CTL1 = ADC12SSEL_1 +ADC12SHS_1 + ADC12SHP ;
  ADC12CTL2 = ADC12RES_2;
  ADC12MCTL0 = ADC12SREF_1 + ADC12INCH_2;
  P2SEL = BIT2;
  ADC12IE = ADC12IE0;
  ADC12CTL0 |= ADC12ENC;

  TA0CCR0 = Aclk/(100) - 1;//328-1=327
  TA0CCR1 = TA0CCR0 - 20;//307
  TA0CCTL1 = OUTMOD_3;
  TA0CTL = TASSEL_1 + MC_1;

  while (1)
  {
    __bis_SR_register(CPUOFF + GIE);
  }
}

#pragma vector=ADC12_VECTOR
__interrupt void ADC12ISR(void)
{
	result=ADC12MEM0;
	ADC12CTL0 |= ADC12SC;
	__bic_SR_register_on_exit(CPUOFF);//CPU OFF mode(i.e.,LMP0)
}

thanks Jens-Michael Gross for such a clean and good explanation.

I changed the code by analyzing in this way

1) First set the ADC clock

ADC12CTL1= ADC12SSEL_1 (ACLK_select)

I checked the page section 20.3.2 ADC12CTL1 Register page 554 slau25e9.pdf of this datasheet which says that the ADCCLK sources can be selected from any one of these ALCK, SMLCK, MDOSC and was not able to find the about the minimum ADC12LCK=400 kHz.

2) ADC12SHT_0=4 there will be 4+13(conversion cycles) =17 that makes ACLK/17

1.9 KHz making 0.5ms

3)Yes, you right ACLK=32768/100=327.68=328 so,timer is set as TA0CCR0=328-1=327
TA0CCR1=307

4) Once the TA0CCR1 reaches 307^th count the SHI triggers the sampling timer. There are 20 Timer ticks in between 307 to 327 which has around 0.6 ms time duration(as timer CLK=32768 =>0.03ms ;20 ticks=20*0.03=0.6ms)

http://e2e.ti.com/cfs-file.ashx/__key/communityserver-discussions-components-files/166/8321.sampcon.JPG

If we look at this sampling working, then let us assume that after 309^nd tick of timer starts the sampling period then it needs 309+17(ADC CLK cycles) so the ADC sampling period+ADC conversion will be finished by the end of 326th tick of timer (here the ADC finishes its 17^th cycle for conversion).

At the 327^th tick of timer the timer resets to ‘0’.Again after the counting starts the ADC sampling start at 307^th tick of timer and process goes.

Is this the way of understanding the ADC sampling?

Isn’t it good to make the difference between CCR0 and CCR1 more than 20 to have than the better working. Is there a limit on this difference?

Can someone correct me if I am wrong in understanding the working in any step?

0 Jens-Michael Gross over 11 years ago in reply to Govardhan Reddy Patancheru

Guru 227245 points

Govardhan Reddy Patancheru said:
was not able to find the about the minimum ADC12LCK=400 kHz.

That's why I said Datasheet/errata sheet. It's not in the users guide, because the users guide (with a few exeptions) doesn't talk about frequency limits or other such details. It talks about concepts only.

that makes ACLK/17

You run the timer from ACLK, but not the ADC. The ADC still runs on the default config of ADC12OSC/MODOSC (which is ~6MHz), divided by 4 (ADC12PDIV)

Once the TA0CCR1 reaches 307th count the SHI triggers the sampling timer. There are 20 Timer ticks in between 307 to 327

But these 20 ticks are a don't care. The ADC has been triggered. Now SAMPCON starts sampling and counts for 4 ADC12CLK ticks, then ends sampling and starts conversion for another 13 ADC12CLK ticks. No matter when (or if at all) the timer output resets.

If you don't set ADC12SHP, then the timer signal starts and ends the sampling phase (and then indeed for 20 timer ticks = 0.6ms), followed by 13 ADC12CLK ticks for the conversion. And ADC12CLK still is 6MHz/6.

Unless you configure the ADC to run with ACLK too (which would be too slow for reasonable results, this has to do with how the ADC works internally), there is no relation between timer ticks (ACLK-based) and ADC12CLK ticks (MODOSC based by default)

Also, I noticed that you set REFON in REFCTL0. The assignment implicitly clears the REFMSTR bit in REFCTL0, rendering all other bits of REFCTL0 void.
This line only coincidentally makes the reference work. Better write REFCTL0&=~REFMSTR;

Finally, make your result variable volatile. All variables that are used in both, main code and ISRs, need to be declared volatile. So the compiler does nto do any optimizations on them, not knowing that an ISR will magically be executed without a function call.

0 Govardhan Reddy Patancheru over 11 years ago in reply to Jens-Michael Gross

Intellectual 840 points

Thanyou for explaining it in such a detailed way.

1)But if the ADC12CLK source is selected as ACLK=32KHz using ADC12SSEL_1 then I guess it will work as below

---let us assume that after 309^nd tick of timer starts the sampling period then it needs 309+17(ADC CLK cycles) so the ADC sampling period+ADC conversion will be finished by the end of 326th tick of timer (here the ADC finishes its 17^th cycle for conversion).

At the 327^th tick of timer the timer resets to ‘0’.Again after the counting starts the ADC sampling start at 307^th tick of timer and process goes.

2)I found out in datasheet CCSF5137 page 64 that the minimum ADC12CLK source is 0.45MHz as I am selecting the internal reference voltage of 2.5V using these lines

ADC12CTL0 = ADC12SHT0_0 + ADC12REFON +ADC12ON + ADC12REF2_5V;

ADC12MCTL0 = ADC12SREF_1 + ADC12INCH_3;

If minimum needed is 450 KHz then I have select Smclk= 1 MHz as ADC12CLK source to get better ADC results.

3)Can I get some explanations regarding this

--How the ADC sampling differ or the output of ADC will differ if ADCLCK source is used as 32.7Khz and if ADC12LCK source is used as 1Mhz (>0.45MHz as mentioned in the datasheet) because when I used 32.7Khz (ACLK) in the above code with ADC12SSEL_1 by feeding a pulse_signal of 1Hz and when saw the output in Matlab by sending the ADC sample value throught the UART found that I was able to get 1Hz pulse signal on matlab plot.

--How the selected ADC12CLK source of ACLK=32768Khx will differ in the working if it is not followed with the datasheet reuirement of >0.45Mhz

Thankyou.

0 Ilmars over 11 years ago in reply to Govardhan Reddy Patancheru

Guru 46710 points

Govardhan Reddy Patancheru said:
--How the ADC sampling differ or the output of ADC will differ if ADCLCK source is used as 32.7Khz and if ADC12LCK source is used as 1Mhz (>0.45MHz as mentioned in the datasheet) because when I used 32.7Khz (ACLK) in the above code with ADC12SSEL_1 by feeding a pulse_signal of 1Hz and when saw the output in Matlab by sending the ADC sample value throught the UART found that I was able to get 1Hz pulse signal on matlab plot.

If you run ADC using clock that is outside specified clock frequency range it is known that very likely ADC will not meet it's specification. How exactly it will not meets it's specification - it is not known. For charge distribution ADC most probably it will mean invalid output bits - not necessarily least significant ones. Basically if you run ADC out of it's specification - you will get some data but bad news is that you can't trust it.

0 Jens-Michael Gross over 11 years ago in reply to Govardhan Reddy Patancheru

Guru 227245 points

Govardhan Reddy Patancheru said:
if the ADC12CLK source is selected as ACLK=32KHz using ADC12SSEL_1

... then the timing will indeed be as you described. But the results won't be reliable. During the 13 conversion steps (13/32768 = 0.4ms) the tiny charge sampled in the sampling capacitor will run off, and the conversion result may be anything, but not correct. This is why the minimum clock for ADC12OSC is 450kHz. The slower you clock the ADC, the less reliable the result will be. But if you clock it too fast, the charge will not have enough time to float back and forth for the charge distribution method used by the ADC. As a result, the conversion results won't be reliable too.

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Minimum time needed for the ADC conversion