DCO MOD and Maximum System Frequency

Well, as you found out yourself, this will run the CPU outside specs. So the official answer would be 'no'. However, you might want to risk it - usually, devices are tested with some safety margin. So it won't stop working on 25.000001MHz. But how much you can exceed the limit without problems (and problems might be subtle at first, growing more serious the more you stray from the specs) is not known.

Also, don't forget REFO tolerance. (if you do use a real 32768Hz crystal, you might as well use a real 25MHz crystal and then be assured that it is precise, stable and not above the specs.)

Thank you,
for answer.
 I use real 7372800 Hz crystal (can’t use 25MHz crystal for the reasons not connected to the MSP430).
I try to understand which maximum frequency for CPU I can get using FLL. Modulator output instantaneous frequency should not exceed Maximum allowable frequency for CPU (25 MHz). If frequency step is about 2 MHz (8%) in range of 25 MHz, then setting frequency less than 23 MHz will guarantee correct instantaneous frequency on the Modulator output at any time. Is it so?
For example FLLN divider = 3, FLLD divider =1, FLLREFDEV = 1 then
DCOCLK = 3 * FLLREF = 3* 7.3728 = 22.18 MHz
The worst case Fdco+1 = 22.18+2 = 24.18 MHz < 25 MHz
The maximum instantaneous frequency of Modulator = 24.18 MHz that < than 25 MHz
Are such settings correct?

Alexey Semenov said:

setting frequency less than 23 MHz will guarantee correct instantaneous frequency on the Modulator output at any time. Is it so?

Yes. Some time ago, I calculated something around 23.4MHz, but this was for a different MSP, so maybe the DCO step size was a bit different..

Note that you can program the DCO for twice the frequency (or 4 times) and use a clock divider (e.g. FLLD and DCOCLKDIV). This reduces the jitter caused by switching between the two frequencies and also narrows the required security margin, so you could go higher. But I never did the math.

In fact, the default 1MHz clock setting runs the DCO on 2MHz (using FLLD=1 -> factor 2) and MCLK runs from DCOCLKDIV (which also uses the FLLD setting to divide SCOCLK back by the same factor)

Note that FLLREVDIV=1 will halve the reference clock and therefore halve the DCO frequency while FLLD=1 will halve the DCO input and therefore double DCO frequency. The difference between FLLD=FLLREFDIV=1 to FLLD=FLLREFDIV=0 is DCOCLKDIV output, but not DCOCLK output (DCO frequency).

Yes, lots of tweaks with many different effects.

Thank, you.