This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Driverlib gives wrong MCLK value

Other Parts Discussed in Thread: MSP430F5529

I have used a code written for MSP430 tutorial to run the MSP430F5529 Launchpad MCLK at 8MHz.

I used the code below as a separate C file to initialize the clock and in the main program it just blinks it every second. Unfortunately when I set a breakpoint and watch the value of "myMCLK ", It shows a value of 8,192,000Hz after initialization. I was expecting to get a value of 8,388,608Hz which which should be the case when we set the value of UCSCTL2 to 249 . Where did this value come from?

// --------------------------------------------------------------------
// myClocks.c  (for lab_04a_clock project)
// --------------------------------------------------------------------

// ACLK is set





//***** Header Files **********************************************************
//#include <stdbool.h>
#include <driverlib.h>
#include "myClocks.h"


//***** Defines ***************************************************************
#define LF_CRYSTAL_FREQUENCY_IN_HZ     32768
#define HF_CRYSTAL_FREQUENCY_IN_HZ     4000000
#define MCLK_DESIRED_FREQUENCY_IN_KHZ  8 * 1000
#define MCLK_FLLREF_RATIO              MCLK_DESIRED_FREQUENCY_IN_KHZ / ( UCS_REFOCLK_FREQUENCY/1024 )   // ratio = 250    , (UCS_REFOCLK_FREQUENCY=32768)


//***** Global Variables ******************************************************
uint32_t myACLK  = 0;
uint32_t mySMCLK = 0;
uint32_t myMCLK  = 0;


//***** Functions **************************************************************
void initClocks(void) {

    // Initialize the XT1 and XT2 crystal frequencies being used
    //  so driverlib knows how fast they are
    UCS_setExternalClockSource(  UCS_BASE,        //This function is called only because UCS_getACLK.. is used. Otherwise remove it
            LF_CRYSTAL_FREQUENCY_IN_HZ,
            HF_CRYSTAL_FREQUENCY_IN_HZ
    );
//
    // Verify if the default clock settings are as expected
    myACLK  = UCS_getACLK(  UCS_BASE );        // only used for checking purposes
    mySMCLK = UCS_getSMCLK( UCS_BASE );
    myMCLK  = UCS_getMCLK(  UCS_BASE );

    // Setup ACLK to use REFO as its oscillator source
    UCS_clockSignalInit( UCS_BASE,
            UCS_ACLK,                                    // Clock you're configuring
            UCS_REFOCLK_SELECT,                          // Clock source
            UCS_CLOCK_DIVIDER_1                          // Divide down clock source by this much
    );

    // Set the FLL's clock reference clock source
    UCS_clockSignalInit( UCS_BASE,
            UCS_FLLREF,                                  // Clock you're configuring
            UCS_REFOCLK_SELECT,                          // Clock source
            UCS_CLOCK_DIVIDER_1                          // Divide down clock source by this much
    );

    // Configure the FLL's frequency and set MCLK & SMCLK to use the FLL as their source
    UCS_initFLLSettle( UCS_BASE,
            MCLK_DESIRED_FREQUENCY_IN_KHZ,               // MCLK frequency
            MCLK_FLLREF_RATIO                            // Ratio between MCLK and FLL's reference clock source
    );

//    // Optional lab step set MCLK to run from REFO
//    // This will make the LED blink very sloooowly in our while{} loop
//    UCS_clockSignalInit( UCS_BASE,
//            UCS_MCLK,                                    // Clock you're configuring
//            UCS_REFOCLK_SELECT,                          // Clock source
//            UCS_CLOCK_DIVIDER_1                          // Divide down clock source by this much
//    );

    // Verify that the modified clock settings are as expected
    myACLK  = UCS_getACLK(  UCS_BASE );    // Only for test purposes
    mySMCLK = UCS_getSMCLK( UCS_BASE );
    myMCLK  = UCS_getMCLK(  UCS_BASE );
}

void initPowerMgmt(void) {
    // Set core voltage level to handle 8MHz clock rate
    PMM_setVCore( PMM_BASE, PMM_CORE_LEVEL_1 );
}

  • Habesha said:
    It shows a value of 8,192,000Hz after initialization. I was expecting to get a value of 8,388,608Hz which which should be the case when we set the value of UCSCTL2 to 249 . Where did this value come from?

    Well, you could step through the code (stepping into the driverlib code) and inspect the calculations and register settings as you go to see where the calculations differ.

    But, my psychic debugging skills make me think the difference is a factor of 1000 vs 1024.

    8388608 / 1024 = 8192

  • Indeed it is a problem with the math in the definitions.

    If you divide (target clock /1000) by (reference clock / 1024) then the result is obviously not correct.

    Why don’t you define the desired frequency in Hz and divide it by (undivided) reference frequency?

    8,000,000/32768 gives a factor of 244 (rounded down by integer arithmetic). Which results in a target frequency of 7,995,392Hz (+- tolerance of the reference and the DCO stepping/modulation jitter)
    With your formula, you get a factor of 250, and 250*32768 is (surprise) 8,192,000Hz.

  • Thanks a lot Jens, I overlooked my mistake on that part and I was spending too much time going through the driverlib functions. 

    I just get rid of the part where I changed it to KHz and removed the error as you suggested and it works. 

    #define MCLK_DESIRED_FREQUENCY 8000000
    #define MCLK_FLLREF_RATIO         MCLK_DESIRED_FREQUENCY / UCS_REFOCLK_FREQUENCY 

**Attention** This is a public forum