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Troubles with SPI clock on MSP430G2955 (and MSP430G2553)

Haroldo Amaral
Expert 1105 points

Other Parts Discussed in Thread: MSP430G2955

Hi,

I'm having troubles of synchronism with the MSP430G2955 (I tried on the G2553 but still happen) when I use the 16MHz clock. When I configure to 1MHz works fine.
I tried to divide to configure the SMCLK using the code:

BCSCTL2 |= DIVS_1;

But occur a lost of synchronism.

When I tried to use the prescaler the lost of synchronism also occur.
The problem is no the slave device, a flash memory because the limit clock is 25MHz. Using a logic analyser i can see the lost of synchronism.
What is the problem?

- My code configuring the SPI and clock in 1MHz and working:

WDTCTL = WDTPW + WDTHOLD;
BCSCTL1 = CALBC1_1MHZ;
DCOCTL = CALDCO_1MHZ;

UCB0CTL1 = UCSWRST;
UCB0CTL0 |= UCMSB + UCMST + UCSYNC + UCCKPL;
UCB0CTL1 |= UCSSEL_2;
UCB0CTL1 &= ~UCSWRST;

This code works fine and I can send and receive data.

- My code adapted to 16MHz, don't working.

WDTCTL = WDTPW + WDTHOLD;
BCSCTL1 = CALBC1_16MHZ;
DCOCTL = CALDCO_16MHZ;
//BCSCTL2 |= DIVS_3; // SMCLOCK /8 = (16 / 8) = 2MHz

UCB0CTL1 = UCSWRST;
UCB0CTL0 |= UCMSB + UCMST + UCSYNC + UCCKPL;
UCB0BR0 = 16; // clock = SMCLK / 16 = 1MHz
UCB0CTL1 |= UCSSEL_2;
UCB0CTL1 &= ~UCSWRST;

In this code, or using the divider to SMCLK the lost of synchronism occur.

  • 0
    Guru 227245 points

    You might be using the wrong polarity or phase. If so, then communication is fragile and only works due to line capacitance and driver delays. On higher speeds, the timings are narrower and communication may break down. Check your settings (not by ‘mode nr’ or ‘bit value’ but by their actual meaning.) Or just try all four possible constellations.

    Also, on higher speeds, line capacitance may affect signal quality to the point the other side won’t see the required signal level in time. Your 16MHz clock speed may turn into a 16MHz sine wave and the slave won’t get a proper clock/data signal anymore or after digital recovery, the resulting clock signal may exceed 25MHz due to an unbalanced duty cycle.

  • 0 in reply to Jens-Michael Gross
    Expert 1105 points

    Jens-Michael Gross, what I don't understand is... If i configure the divisor to the submain clock, or use the prescaller the clock won't be 16MHz but the new value, correct?

    Even setting the master clock in 1MHz, if I change the SMCLK or the prescaller to a lower value the communication don't work fine, and in this case the problem is not a high clock.

  • 0 in reply to Haroldo Amaral
    Guru 227245 points

    Indeed, you’re right. With the additional /16 divider it should be same output.

    It may be that on your MSP, the calibration values for 16MHz are wrong. You can check SMLCK frequency by enabling SMCLK output on a port pin and check it with a scope. Really 16MHz?

    Also, 16MHz CPU core frequency requires a higher supply voltage.

    Can you post the logic analyzer result (for both, 16 and 1MHz)

    Also, what exactly do you mean with lost synchronization? MOSI and clock are generated by hardware from the same clock signal. There can be no synchronization loss. So I interpreted it as the slave is not getting data right or master is not getting slave response right. Where phase and polarity come in.

    However, with effectively the same bit clock, the remaining difference is the CPU speed. Maybe your code doesn’t properly wait for the end of a transaction. On SPICLK==MCLK, after 8 CPU clock pulses, the transfer is done. The CPU can’t stuff the SPI as fast as it is transmitting. Which is no problem when being master.
    But with 16MHz MCLK, you have 128MCLK cycles per byte. IF the code doesn’t properly check the SPI status, then you’re stuffing too much too fast into the transmitter and communication fails.
    I’d have to see your transfer code to check.

  • 0 in reply to Jens-Michael Gross
    Prodigy 135 points

    Hi!

    I am trying to communicate between two MSP430G2955 using the SPI(Master/slave) protocol. Currently, I am using the example codes provided in the resource explorer. However, I am not able to see any data on the logic analyzer. Could someone point out the possible errors.

    The hardware connections are as follows:

    MASTER      SLAVE
    MOSI--->MISO

    MISO--->MOSI

    CLOCK out-->CLOCK in

    Chip select-->RST/NMI

    Any leads would be appreciated.

    Thanks!

  • 0 in reply to Aashna Mittal
    Guru 227245 points

    Are you switching the port pins to module mode? Default is software-controlled I/O.

    Also, making a chip select by controlling the slave’s RST pin is a bad idea. After you ‘select’ the chip (with the not typical high level, usually, CS is asserted low and de-asserted high), the slave needs to boot before it can respond. This takes quite some time. The slave should be already running and waiting for the chip select signal.

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