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SPI on msp430g2553 using ccs5 one click examples

Other Parts Discussed in Thread: MSP430WARE

Hi I am new to this forum.

I did try my best to find an answer, but if the answer is just there please just tell me.

I CCS5.5,  I chose from the one click projects (in TI resource explorer)  msp430g2xx3_uscia0_spi_09 and downloaded it to the Launchpad. 

here is the code of the project that is generated  :

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*******************************************************************************
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* MSP430 CODE EXAMPLE DISCLAIMER
*
* MSP430 code examples are self-contained low-level programs that typically
* demonstrate a single peripheral function or device feature in a highly
* concise manner. For this the code may rely on the device's power-on default
* register values and settings such as the clock configuration and care must
* be taken when combining code from several examples to avoid potential side
* effects. Also see www.ti.com/grace for a GUI- and www.ti.com/msp430ware
* for an API functional library-approach to peripheral configuration.
*
* --/COPYRIGHT--*/
//******************************************************************************
// MSP430G2xx3 Demo - USCI_A0, SPI 3-Wire Master Incremented Data
//
// Description: SPI master talks to SPI slave using 3-wire mode. Incrementing
// data is sent by the master starting at 0x01. Received data is expected to
// be same as the previous transmission. USCI RX ISR is used to handle
// communication with the CPU, normally in LPM0. If high, P1.0 indicates
// valid data reception.
// ACLK = n/a, MCLK = SMCLK = DCO ~1.2MHz, BRCLK = SMCLK/2
//
// Use with SPI Slave Data Echo code example. If slave is in debug mode, P3.6
// slave reset signal conflicts with slave's JTAG; to work around, use IAR's
// "Release JTAG on Go" on slave device. If breakpoints are set in
// slave RX ISR, master must stopped also to avoid overrunning slave
// RXBUF.
//
// MSP430G2xx3
// -----------------
// /|\| XIN|-
// | | |
// --|RST XOUT|-
// | |
// | P1.2|-> Data Out (UCA0SIMO)
// | |
// LED <-|P1.0 P1.1|<- Data In (UCA0SOMI)
// | |
// Slave reset <-|P1.5 P1.4|-> Serial Clock Out (UCA0CLK)
//
//
// D. Dang
// Texas Instruments Inc.
// February 2011
// Built with CCS Version 4.2.0 and IAR Embedded Workbench Version: 5.10
//******************************************************************************
#include <msp430.h>

unsigned char MST_Data, SLV_Data;

int main(void)
{
volatile unsigned int i;

WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer
P1OUT = 0x00; // P1 setup for LED & reset output
P1DIR |= BIT0 + BIT5; //
P1SEL = BIT1 + BIT2 + BIT4;
P1SEL2 = BIT1 + BIT2 + BIT4;
UCA0CTL0 |= UCCKPL + UCMSB + UCMST + UCSYNC; // 3-pin, 8-bit SPI master
UCA0CTL1 |= UCSSEL_2; // SMCLK
UCA0BR0 |= 0x02; // /2
UCA0BR1 = 0; //
UCA0MCTL = 0; // No modulation
UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
IE2 |= UCA0RXIE; // Enable USCI0 RX interrupt



P1OUT &= ~BIT5; // Now with SPI signals initialized,
P1OUT |= BIT5; // reset slave

__delay_cycles(75); // Wait for slave to initialize

MST_Data = 0x01; // Initialize data values
SLV_Data = 0x00;

UCA0TXBUF = MST_Data; // Transmit first character

__bis_SR_register(LPM0_bits + GIE); // CPU off, enable interrupts
}

// Test for valid RX and TX character
#pragma vector=USCIAB0RX_VECTOR
__interrupt void USCIA0RX_ISR(void)
{
volatile unsigned int i;

while (!(IFG2 & UCA0TXIFG)); // USCI_A0 TX buffer ready?

if (UCA0RXBUF == SLV_Data) // Test for correct character RX'd
P1OUT |= BIT0; // If correct, light LED
else
P1OUT &= ~BIT0; // If incorrect, clear LED

MST_Data++; // Increment master value
SLV_Data++; // Increment expected slave value
UCA0TXBUF = MST_Data; // Send next value

__delay_cycles(50); // Add time between transmissions to
} // make sure slave can keep up

Here is my problem :

Right now the launchpad is not wired to any other device, and still the red LED indicating that a valid response was received is is blinking rapidly.   It seems strange  that the interrupt is even reached, if nothing is connected.

Morever the red light indicated that a valid echo has been received, how is that possible ?

I'm trying to learn SPI through  experimenting with the launchpad can anyone direct me.

Thanks in advance. 

  • SPI is a bi-directional synchronous protocol. When the master generates a clock pulse, the slave will sample a data bit form the MOSI line and the master will sample a bit form the MISO line.
    If there is no slave listening, the master won’t notice. If there is no slave talking, the master will sample a ‘1’ as if the slave were sending it. Detection of an attached slave has to be done on high-level protocol level.

    As a matter of fact, the master will ‘receive’ a byte and enter the ISR, even if the port pins haven’t been selected for module usage and are still inactive GPIO.

    Most more complex slaves will not give an 0xff “idle” answer, so if 0xff is received, the software can notice that this is not a valid response. But that’s a high-level probability analysis and has nothing to do with the low-level SPI connection.

  • Thank you for the clear answer !

    I will now proceed to test the full set up, as described in the example.

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