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MSP430FR5969 FRAM operation and instruction question

Xiaowei Bai1
Intellectual 1205 points

Other Parts Discussed in Thread: MSP430FR5969

Hi,

I have some questions of msp430fr5969 as below:

1, In msp430fr5969 user's guide page 253 5.7 described as below

" 5.7 FRAM Write Back
All reads from FRAM requires a write back of the previously read content. This write back is performed
under all circumstances without any interaction from a user."

My qustion is why FRAM need writ back opration? as we all know the FRAM is the nonvolatile memory and it don't like DRAM need refresh. I think this operation have some risk when power sudden off during reading FRAM data.

2, How much time are needed of execute one MSP430 instruction and where I can find its document?

  • 0
    Guru 14640 points

    I did a google search on "fram basics" and found this:

    http://www.edn.com/design/systems-design/4394387/4/FRAM-MCUs-For-Dummies--Part-1

    I do not have a copy of the book, but it may explain a lot of your questions. The excerpt in the edn article was pretty good...

  • 0
    Guru 16361 points

    Xiaowei Bai1 said:

    Hi,

    I have some questions of msp430fr5969 as below:

    1, In msp430fr5969 user's guide page 253 5.7 described as below

    " 5.7 FRAM Write Back
    All reads from FRAM requires a write back of the previously read content. This write back is performed
    under all circumstances without any interaction from a user."

    My qustion is why FRAM need writ back opration? as we all know the FRAM is the nonvolatile memory and it don't like DRAM need refresh. I think this operation have some risk when power sudden off during reading FRAM data.

    2, How much time are needed of execute one MSP430 instruction and where I can find its document?

    1) It's not very clear from that section of the documentation, but I suspect the need for write back is caused by the FRAM cache. (EDIT: Incorrect, see Katie Pier's post below)

    2) See section 4.5.1.5 (MSP430 Instruction Execution) of the User's Guide for instruction cycle count listings. You will also need to account for FRAM wait states if using MCLK frequencies above 8MHz.

  • 0
    TI__Guru* 83021 points

    Hi Xiaowei,

    The app note www.ti.com/lit/pdf/slaa526 MSP430FR57xx FRAM Quality and Reliability section 1.3 addresses this topic:

    "In the process of reading the data, the crystal that is polarized in the direction of the applied field loses its current state [2]. Therefore, every read is accompanied by a write-back to restore the state of the memory location. With TI's MSP430 FRAM MCUs, this is inherent to the FRAM implementation and is transparent to the application. The write-back mechanism is also protected from power loss and is ensured to complete safely under all power conditions. The MSP430FR57xx power management system achieves this by isolating the FRAM power rails from the device supply rails in the event of a power loss. The FRAM power circuitry also uses a built-in low-dropout regulator (LDO) and a capacitor that store sufficient charge to complete the current write-back in the event of a power failure [3]."

    Basically, FRAM reads are done by writing and detecting the change in state or not to determine if bits were 0 or 1 (destructive read) - this is simply a result of the physical nature of all FRAM technology, not just the FRAM in the MSP430, so you can find more details on Wikipedia, in technical journals/papers, etc on FRAM. Then there is a write back cycle that happens to re-write the data you just read. In the MSP430 FRAM devices, there is some internal circuitry to ensure that the write-back operation will be guaranteed to complete even if power is lost, so that this is not a concern. All of this happens transparent to the user - no special care needs to be taken.

    For question 2 about instruction times, you can find this information in the user's guide: www.ti.com/lit/pdf/slau367 chapter on the CPUX core. You can see in section 4.5.1.5 a section discussing the exectution time in MCLK cycles of different types of instructions.

    Regards,

    Katie

  • 0 in reply to Katie Pier
    Guru 12966 points

    Short answer for #2, it can run zero-wait-state up to 8MHz (125ns).  Above that it will use wait-states and/or internal caching to improve performance.  Also on the FR5969, you have to explicitly set the wait states before ramping MCLK up above 8MHz.

  • 0
    Guru 34973 points

    Xiaowei Bai1 said:

    2, How much time are needed of execute one MSP430 instruction and where I can find its document?

    It is complicated. Let say that only MSP430x2xx devices have cycle number per instruction, correct, as per datasheet.
    On MSP430F5xx devices, read-modify-write instruction will add waiting states, and information about this can't be found in any datasheet.
    Moving code on MSP430FR5xx from FRAM to RAM and execute it from there, will eliminate FRAM waiting states, but this will not clear doubts about number of cycle per instruction, because when I changed two NOP's with JMP $+2 my bit-banging code was not working correct anymore.  Again, no info about this in any datasheet.
  • 0
    TI__Intellectual 1205 points

    Hi, All

    Thanks very much for your kind help to understand my question, I think I have known it. thanks again!

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