This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

MSP430G2553 SPI mode

hello professors,

I'm using two g2553 chips to achieve the communication between each other.  I connected p1.5(UCB0CLK), p1.6(SOMI), p1.7(SIMO), VCC, and GND to each other, and the initialization function of SPI is as followed:

Master chip:

void Init_USCI_spi()
{
    P1SEL |= BIT5 + BIT6 + BIT7;  //configure ports
    P2SEL |= BIT5 + BIT6 + BIT7;
    
    UCB0CTL1 |= UCSWRST;  //enable, usci logic held in reset state
    UCB0CTL1 |= UCSSEL_2;  //SMCLK
    UCB0CTL0 |= UCCKPL + UCMST + UCMODE_0 + UCSYNC + UCMSB;  //3-pin spi master, slave mode
    UCB0BR0 |= 0x02;
    UCB0BR1 = 0;
    
    UCB0CTL1 &= ~UCSWRST;
    IE2 |= UCB0TXIE;
    //IE2 |= UCB0RXIE;
   
}

Slave chip:

void Init_USCI_spi()
{
    P1SEL |= BIT5 + BIT6 + BIT7;  //configure ports
    P2SEL |= BIT5 + BIT6 + BIT7;
    
    UCB0CTL1 |= UCSWRST;  //enable, usci logic held in reset state
    UCB0CTL1 |= UCSSEL_2;  //SMCLK
    UCB0CTL0 |= UCCKPL + UCMODE_0 + UCSYNC + UCMSB;  //3-pin spi master, slave mode
    UCB0BR0 |= 0x02;
    UCB0BR1 = 0;
    
    UCB0CTL1 &= ~UCSWRST;
    //IE2 |= UCB0TXIE;
    IE2 |= UCB0RXIE;
   
}

However, the slave cannot receive the data from the master, I have no idea ahout the problem, is my code correct? really thank you for giving me the suggestion, thanks for your time


Best regards

  • You don’t need to set UCB0BR in slave mode. Clock signal comes from master.
    Besides this (and it doesn’t hurt), the init seems to be okay.

    However, depending on startup timing, the slave may ‘see’ the port pin init of the master as part of a transmission. Normally, the master uses a chip select pin to sync with the slave: if it goes high, the slave resets the USCI, preparing for the next transmission. (in theory, when CS is high, the slave should shut off its output and ignore any clock signals, but if you only have one case, this part can be omitted) Before starting the transfe,r the master will then pull CS low. And high again after the transfer is completed (be sure that the last byte has really been sent, not just written to TXBUF)
    You only posted the init code, not the actual transfer. Or the clock init code.
    You enable interrupts. Do you have ISRs to handle them?

  • Hello Michael,


    sorry to gvie you the response late.

    Here is my interrupt code in master mode and slave mode:

    This is master chip which sends the data to the slave chip

    int main (void)
    { 
    
    while(1)
    {
    while ((IFG2 & UCB0TXIFG) == 0); 
    // wait while not ready / for RX
    UCB0TXBUF = 0x31;   
    }  
    
    }

    This is slave chip , try to receive the data from the master chip

    #pragma vector=USCIAB0RX_VECTOR
    __interrupt void USCI0RX_ISR(void)
    {
    
      
      /*******SPI slave-mode**********/
      
      if(UCB0RXBUF >= 0x30 && UCB0RXBUF <= 0x39)  
      {
        spi_uart |= 1;   //enable the uart mode
        P1OUT ^= BIT0;  //toggled green led  
        receive_r1[test++] = UCB0RXBUF;  //receive the data in spi mode
                                         //buffer receive_r1 will then transfer to the tx in uart mode
        if(test == sizeof (receive_r1) -1)
        { 
         IE2 |= UCA0TXIE;   //enable the tx in spi mode
         IE2 &= ~UCB0RXIE;  //disable the spi rx
         test=3;  
        }
       
      }

    but the slave cant get any response from the master chip... is there something wrong with my configuration?

    Thanks for your time

    Best regards
  • The master main code you posted does not do any port initialization. At power-up, all MSP port pins are GPIO inputs. You need to switch them to UART mode (PxSEL).  Also, it doesn’t initialize the USCI.
    So you definitely should call the Init_USCI_SPI in the master main
    J

    I’m not quite sure what your slave ISR shall do. You can have USCIA0 and USCIB0 active at the same time, and receive/send simultaneously. No need to switch the enable bits on and off. You need to check the RXIFG and TXIFG flags before you read RXBUF or write to TXBUF, to determine which one has triggered the interrupt.

**Attention** This is a public forum