can't get the CPU clock lower than 0.3 MHz

Joerg Hohensohn said:

The chip is controlled by a 32 kHz crystal, which seems to be common. The crystal deliveres the 'ACLK' clock, which is OK. With this controller, the CPU can't be clocked from ACLK directly, I have to use the internal RC oscillator and the FLL multiplier unit. There's a setting for oscillator range in register SCFI0, but the default is already correct for the slow range.

 Hi From user family on FLL section:

MCLK: Master clock. MCLK is software selectable as LFXT1CLK,
VLOCLK, XT2CLK (if available), or DCOCLK. MCLK can be divided by 1,
2, 4, or 8 within the FLL block. MCLK is used by the CPU and system.

 So you can run cpu at VLOCLK ~12KHz low precision ultra low power rc oscillator

LFXT1 so it can be run @32KHz

 DCO/divider, low range of DCO is 300KHz so low from this is 300/8 near 37.5KHz

From my understanding, the MSP430F425 has a more limited FLL module (see figure 5-2 in SLAU056L document). For MCLK, the only option is to use DCOCLK. There's no VLOCLK nor XT2CLK , also no path to LFXT1CLK.

Is the DCO in fact limited to >300 kHz? Where is that documented? How could I divide that by 8 as you mention?

Thanks,

Jörg

Now I get it. With the unconfirmed information that the DCO has to run above 300 kHz, the configurable loop division with the FLLDx bits of the SCFI0 register makes sense. You need that to increase the DCO frequency when using the lower output frequencies.

Make sure that bit DCOPLUS of register FLL_CTL0 is off, so you get the divided frequency at the output, not the raw DCO frequency. The FLLDx setting multiplies the oscillator clock, while at the same time preserving the output frequency.

In C code, my initialization to 65.536 kHz now look like this:

    SCFQCTL = SCFQ_64K; // slowest frequency
    SCFI0 = FLLD_8; // DCO can't run below ~300kHz, compensate by loop divider

Joerg Hohensohn said:

Is the DCO in fact limited to >300 kHz? Where is that documented? How could I divide that by 8 as you mention?

slau056l.pdf page 290 this is the Family Users Guide rev L

 I suppose you find how to set clock source.

 If all is Ok please check verify'd so this thread can be treated as closed.

Joerg Hohensohn said:

MCLK, the only option is to use DCOCLK. There's no VLOCLK nor XT2CLK , also no path to LFXT1CLK

 You are right, I moved page when I was answering about.

 No oscillator nor selection, but low range at 300KHz and divider from FLL loop.

 This chip has quite limited FLL section but not range of oscillator.

Meanwhile I found that the DCO is still not locked to the crystal with my above setting, and also with the next higher SCFQCTL value. Ice spray makes it run away.

I have to set N=2, which should give me 3 * 32768 Hz = 98.3 kHz. Strange: In fact I measure it slower (93.4 kHz), but it seems locked.

The FLLDx bit description of the SCFI0 register (page 302 of SLAU086L) sugest the DCO won't go below 0.65 MHz, with the FLLDx divider of 8 this makes 81 kHz. So I'm indeed on the next possible setting.

Case not closed, I'd like to re-phrase the subject to "can't get the CPU clock lower than 90 kHz"...

Joerg Hohensohn said:

Meanwhile I found that the DCO is still not locked to the crystal with my above setting, and also with the next higher SCFQCTL value. Ice spray makes it run away.

 Are you sure not spray also the crystal?

 This cut is more stable at design temperature but change a lot if you move away and frequency change in a non linear manner.. so be sure you are cooling or warming just processor and not XTAL too. Also take care of capacitance variation influence resonance load also resulting in a shift of frequency.

 Sorry I cannot help more than this I don't own a 425 hardware to experiment on.

Yes, thanks, this matches with my observation.

I'm now clocking with 98 kHz as you describe, by using factor 3. When going below the oscillator is not tracked and stays at about 300 kHz. I can exploit the /8 division and get indeed 37.5 kHz, but it's too unstable to be useful.

Jörg