MSP430F5338 UART

In your code, you enable RX and TX interrupts. This means you tell the CPU to execute an ISR when the interrupt happens. Which only makes sense when you have ISRs for handling these events (but you don’t). However, setting the IS bits is futile because they are automatically reset as long as SWRST is set.
Also, you did not set GIE to globally enable the interrupt mechanism.
TXIFG and RXIFG are sent independently of the TXIE/RXIE bits – they just don’t cause any interrupt if the IE bits are not set.

 UCAxMCTL is not a multiplication factor, but a modulation pattern. Since 32768/9600 = 3.4133 and a bit can only have an integer multiple of the clock, this pattern controls which bits are shorter (3, as you wrote UCA0BR) and which bits shall be longer (3+1), so that the average bit time is 3.4133 (or as close as this algorithm can come to it).

 At first glance, the code looks good. However, what doe sit do after the second while?
The first while is superfluous. After clearing SWRST, TXIFG is always set immediately. After writing to TXBUF (when the USCI was previously idle), TXIFG is immediately set again as soon as the sending of the first byte has begun (the next clock pulse arrived). So the second while is exited before even the start bit of the first is transmitted. Depending on what the code does after the second while, ti may be that the system shuts down before anything goes out.