PWM MAX frequency

It depends on desired granularity of PWM output

If you want your PWM to be regulated with granularity of 1%, then Fpwm max will be 10kHz;

If 10% granularity is enough for your application, then Fpwm max will be 100kHz.

On your device there are 4 timers available that can be used in PWM mode: TA0-TA2, TB0.

Thanks Serge,

Can you please tell me in which formula to be used to calculate the Fpwm? I am new to PWM that's why i am asking this.

And regarding PWM channels if using a single PWM channel (ex:TA0) we can control 4 different devices connected to the pins  ( 36-P1.2, 40-P1.6 ), ( 37-P1.3, 41-P1.7 ), ( 38-P1.4 ), ( 39-P1.5 ) or 6 different devices for each pin.

Thanks in Advance

Fpwm = Ftclk/(N+1)

where

Fpwm - Frequency of PWM on output pin;

Ftclk - Timer input clock frequency;

N - value written to TAxCCR0 register. 

The number of PWM channels per timer is determined as the number of CCR registers except CCR0. Each channel usually has corresponding output, which is marked as DEVICE OUTPUT SIGNAL in Timer Signal Connections table in data manual for the device. For example, for TA0 there are 5 outputs: TA0.0, TA0.1, TA0.2, TA0.3, TA0.4. Some of these outputs can be routed to several pins, like in your example above - TA0.1 output is routed to pins 36 and 40.

TA0.0 output has very limited capabilities for PWM generation which are described in family data manual slau208n.pdf, page 467, so normally it is not used for PWM.

Thanks Serge,

As per your previous reply my understanding is " Timer TA0 has 7 PWM channels including CCR0" like that for other timers also. So that we can able to control one device in the CCR0 pin 35-P1.1 also am i wright? If not please clarify.

And also is there any sample  programs available to produce a variable duty cycle from (0 - 100)%. Or any clue about how to generate the variable duty cylce for a particular PWM frequency.

Thanks in Advance.

 

Timer TA0 has 5 CCR channels including CCR0. Only 4 of these 5 can be used for PWM: TA0.1, TA0.2, TA0.3, TA0.4.

You can not use pin 35 (which is TA0.0) for PWM.

The sample program is below (it is from TI code samples for TA0):

//*******************************************************************************
//  MSP430F552x Demo - Timer0_A5, PWM TA1.1-2, Up Mode, DCO SMCLK
//
//  Description: This program generates two PWM outputs on P1.2,P1.3 using
//  Timer1_A configured for up mode. The value in CCR0, 512-1, defines the PWM
//  period and the values in CCR1 and CCR2 the PWM duty cycles. Using ~1.045MHz
//  SMCLK as TACLK, the timer period is ~500us with a 75% duty cycle on P1.2
//  and 25% on P1.3.
//  ACLK = n/a, SMCLK = MCLK = TACLK = default DCO ~1.045MHz.
//
//                MSP430F552x
//            -------------------
//        /|\|                   |
//         | |                   |
//         --|RST                |
//           |                   |
//           |         P1.2/TA0.1|--> CCR1 - 75% PWM
//           |         P1.3/TA0.2|--> CCR2 - 25% PWM
//
//   Bhargavi Nisarga
//   Texas Instruments Inc.
//   April 2009
//   Built with CCSv4 and IAR Embedded Workbench Version: 4.21
//******************************************************************************

#include <msp430.h>

int main(void)
{
  WDTCTL = WDTPW + WDTHOLD;                 // Stop WDT
  P1DIR |= BIT2+BIT3;                       // P1.2 and P1.3 output
  P1SEL |= BIT2+BIT3;                       // P1.2 and P1.3 options select
  TA0CCR0 = 512-1;                          // PWM Period
  TA0CCTL1 = OUTMOD_7;                      // CCR1 reset/set
  TA0CCR1 = 384;                            // CCR1 PWM duty cycle
  TA0CCTL2 = OUTMOD_7;                      // CCR2 reset/set
  TA0CCR2 = 128;                            // CCR2 PWM duty cycle
  TA0CTL = TASSEL_2 + MC_1 + TACLR;         // SMCLK, up mode, clear TAR

  __bis_SR_register(LPM0_bits);             // Enter LPM0
  __no_operation();                         // For debugger
}

In order to produce duty cycle from (0-100)%, you'll have to write corresponding values to TA0CCR1, TA0CCR2. For the example above, these values are in a range of (0-511). Value 0 corresponds to 0% duty cycle, 511 - 100% duty cycle. The top value (511) can not exceed the value written to TA0CCR0, which defines Fpwm.

Prakash Balagangatharan said:

control one device in the CCR0 pin 35-P1.1 also

Yes and no.
CCR0 is used to limit the timer count in case (which is the usual case) you don’t want to be a whole timer cycle (65536 clock ticks) be a PWM cycle.

If CCR0 controls the PWM frequency, it cannot at the same time control the duty cycle of its output. In this case, all you can get is a 50% DC signal with half PWM frequency, or a one-tick-pulse at the end of each PWM cycle, but not a PWM signal.