MSP430 maximizing pin speed

Have you checked the generated assembly code to see what it's doing? First thing I would check is how the de-referencing is being done. Is there a reason you can't just use the actual register names?

Another thing... you could set the output pin value low ahead of time (before the while() loop) because it has no effect when the port pin is set to input. Then you only have to switch direction.

Why not using an external logic gate?

As using the same pin to sense a state and then turn-it around to do a hard low will always take time.

I assume the trace is open-drain as playing with bi-directional signals could cause harm unless
you use a 2.2K pull-up resistor as the only logic high.

Then only using DIR as 0/1 state should speed it up, as a Low can be pre-set.
But what you trying to do is not the job of a mcu but a gate.

But need more info what the device is that is pulling it low etc.
And what you are trying to accomplish.

Hopefully, the external thing that drives the pin low is an "open collector" kind of thing. In that case, you can configure that pin as input with internal pull-up. When you detect that is going low, simply change from pull-up to pull-down. I think this can be accomplished <1 usec. Too much capacitance on that pin can be a drag. 

I actually made changes similar to what you suggested:  I moved the resistor disable and set to output before the while loop, so now I only have to change the output direction.  I am now able to complete the task in 2.2 microseconds, sadly just a little too long.  I'm going to go back and test the microcontroller if I put an edge-triggered interrupt here instead of a while loop, as I am relatively sure the while loop is the main cause of the delay.

A IRQ will also take at least 2uS, as it has to store PC and Status to stack before it can start any code.

Using the edge as a clk for timerA0 input would probably be fastest way.
But that you want to use the same pin makes it harder, can you P1.0/TA0CLK and P1.5/TA0.0 instead?

So instead, explain what is it your are trying to accomplice
and I tell you the external gate design you need. ALS gates can do it 10nS

I can use any pin on the board realistically (1.0-1.7, 2.0-2.5).  My goal is for the microcontroller to detect an external master device pull the line low, and hold it low before a 2microsecond period expires.  I am curious as your ALS gate suggestion, although I actually solved the problm by chaning my code to the following:

// unsigned int BIT4 = ~ow->pin;

*(ow->port_ren) &= BIT4;

*(ow->port_out) &= BIT4;

while(*(ow->port_in) & BIT4);

*(ow->port_dir) |= BIT4;

By derefencing the pointer ahead of time, I was able to detect and hold the line low in my desired 2 us period

> external master device pull the line low

If you can tell me the master device name?

The Picture attached assumes your device is Open Collector type.

What the two 10K series resistor does:
1: Protect the msp430 from a short if having its pin as output-high while device is driving it low.
2: MSP430 will win over the Buffer IC pull-ing the line low.

When the OpenDrain Buffer gets a low on its input it will sink its output to gnd

P1.4 as Input you can detect the state change, but no need to hurry as the buffer handles its own self-latching in nS.
When you are ready to release the latched-low, put pin P1.4  as output high for a few uS
You may have to do this at power-up too as to reset the latch.

Part: http://www.mouser.com/ProductDetail/Texas-Instruments/SN74LVC1G07DBVR/?qs=sGAEpiMZZMuiiWkaIwCK2WAncryyStC7BmX24YKQilU%3d
I have not tested the below circuit.
For extreme fast signaling, Logic w/ enable may be better as to eliminate 10k series-resistors
as they probably induce 50nS+ delay, but on other hand they do filter the signal a little.
Using 2K and short traces will reduce delays too, as resistor+trace-capacitance is the RC filter delay.

Many years ago, I developed a bi-directional OC driver for I2C and interrupt lines. It did follow the input level on one end and driving it to the other, without locking/looping. It uses two XOR gates and two inverters.
On one end could be an edge-driven monoflop for the 2µs. So the input would be forwarded to the monoflop, reset it, and when the input signal goes high, it will be kept low by the monoflop until it expires too. Whatever happens first.

A plain hardware solution.