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MSP430F5340 SPI Slave on UCA0

Yvan Pearson1
Prodigy 140 points
Other Parts Discussed in Thread: MSP430F5340

I'm using a MSP430F5340 to implement a simple spi slave. The msp430 is running at ~1Mhz (default clock). The SPI master is a Aardvark I2C/SPI Host Adapter on spi mode0 at 125kHz.

I seem to be getting the right RXbuff. 

Here is what I am seeing:

master send: 0xab

slave rx: 0xab

fill tx with 0xab

wait 1 second or more

Trigger another byte transmission.

master send: 0xab

slave rx: 0xd5  !!

fill tx with 0xd5

wait 1 second or more

Trigger another byte transmission.

master send: 0xab

slave rx: 0xf6

fill tx with 0xf6

My code is dead simple.A lot of it was from the TI code example. My only suspicion is 125kHz is somehow too fast. Any ideas?

#include "msp430.h"
unsigned char reg;
void main(void)
{
reg = 0x01;
WDTCTL = WDTPW+WDTHOLD; // Stop watchdog timer

/* reset USCI state machine */

UCA0CTL1 |= UCSWRST;

/* cs input */
//P3DIR &= ~BIT2;
P3SEL |= BIT2;

/* simo input */
//P3DIR &= ~BIT3;
P3SEL |= BIT3;

/* somi output */
//P3DIR |= BIT4;
P3SEL |= BIT4;

/* sclk input */
//P2DIR &= ~BIT7;
P2SEL |= BIT7;

// MSB 8-bit SPI slave
UCA0CTL0 |= UCCKPH + UCMSB + UCSYNC;// + UCMODE1;

/* start USCI state machine */
UCA0CTL1 &= ~UCSWRST;
UCA0IE |= UCRXIE;
UCA0IE |= UCTXIE;

__bis_SR_register(LPM3_bits + GIE);
}

// Echo character

void USCI_A0_ISR(void) __interrupt[USCI_A0_VECTOR]
{
switch(UCA0IV)
{
case 0:break;
case 2:
reg = UCA0RXBUF;
break;
case 4:
UCA0TXBUF = reg;
break;
default: break;
}
}

Thanks for writing !

  • 0
    Prodigy 140 points

    I found a fix. it may be an issue with the Aardvark. I tested the different Aardvark modes versus the msp430 modes and discovered some modes work and other modes do not work. Here is what I found:

    // MSP430F5340 UCA0 modes do not work with ANY Aardvark GUI modes (v3.56)
    //UCA0CTL0 |= UCMSB + UCSYNC + UCMODE1 + UCCKPH /*+ UCCKPL*/;
    //UCA0CTL0 |= UCMSB + UCSYNC + UCMODE1 /*+ UCCKPH*/ + UCCKPL;


    /* Works with Aardvark [MSB, Rising/Falling, Setup/Sample] */
    // UCA0CTL0 |= UCMSB + UCSYNC + UCMODE1 + UCCKPH + UCCKPL;

    // Works with Aardvark [MSB, Rising/Falling, Setup/Sample]
    UCA0CTL0 |= UCMSB + UCSYNC + UCMODE1;

    Go figure, let me know if someone can provide insight to this.

    Thanks,

  • 0 in reply to Yvan Pearson1
    Guru 227245 points

    As you discovered, there are four possible modes. Clock polarity determines, whether the clock is active-high or active-low. Phase means whether signal is sampled at the edge where the clock goes active or at the edge where to clock goes inactive.

    Polarity and Phase need to match on both, slave and master. However, if the polarity is wrong, and the phase is wrong too, the two somewhat compensate and it might still work. However, it is very timing critical then.

    It should be noted, that the TI notation of clock polarity is different from (inverse to) the Motorola notation.

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