setup clocks MSP4305137

I'm currently attempting to set up my clocks for my system and I'm getting a little confused I believe my system is set up to run SMCLK at 4MHz, but when using the USCI it would appear that SMCLK is running at 16MHz.

I use the following code to set up my clocks:

			UCSCTL3 |= SELREF_0;                      // Set DCO FLL reference = XT1
			UCSCTL4 |= SELA_0+SELS_4+SELM_4;          // Set ACLK = XT1, SMCLK = DCOCLK & MCLK = DCOCLK

			__bis_SR_register(SCG0);		  // Disable the FLL control loop
			UCSCTL0 = 0x0000;                         // Set lowest possible DCOx, MODx
			UCSCTL1 = DCORSEL_5;                      // Select DCO range 2.5-6MHz operation
			UCSCTL2 = FLLD_1 + 249;                   // Set DCO Multiplier for 4MHz
								  // (N + 1) * FLLRef = Fdco
								  // ((249 + 1) * 32768)/2 = 4MHz
								  // Set FLL Div = fDCOCLK/2
			__bic_SR_register(SCG0);		  // Enable the FLL control loop

			// Worst-case settling time for the DCO when the DCO range bits have been
			// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
			// UG for optimisation.
			// 32 x 32 x 4 MHz / 32,768 Hz = 125000 = MCLK cycles for DCO to settle
			__delay_cycles(125000); 
		/*****************************************************************************************************/
			// Loop until XT1,XT2 & DCO fault flag is cleared
			do
			{
				UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
				// Clear XT2,XT1,DCO fault flags
				SFRIFG1 &= ~OFIFG;                      // Clear fault flags
			} while (SFRIFG1 & OFIFG);                  // Test oscillator fault flag

However inorder to get 9600 baud out of the micro I have to use the following settings:

    UCA0CTL1 = UCSSEL_2;
    UCA0BR0 = 0x82;
    UCA0BR1 = 0x06;
    UCA0MCTL = UCBRS_6 + UCBRF_0

which would imply that SMCLK is running at 16MHz.

XT1 is connected to an external crystal at a speed of 32768KHz. is there something wrong in the way I am setting up my clock?