can't able to generate PWM with defined duty cycle

This has nothing to do with programming but with math.

When your max count (CCR0) = 20 equals to 100% duty, then every count is 1/20 is also 1/20 of the duty% is 100/20 = 5%. 17 will give also 17*5 = 85% and 18 will give you 18*5 = 90%.

To get steps of 1%, CCR0 should be at least 100 (-1), but then to keep your frequency you have to increase your clock frequency.

Leo Bosch said:

To get steps of 1%, CCR0 should be at least 100 (-1), but then to keep your frequency you have to increase your clock frequency.

so if i am not getting step size as1 like as 2 or 0.4 or some other values means i can't able to get the exact duty cycle value am i write? pls clarify.

Also if look into the frequency that also varies not the given one Why? Is this also has any dependent like step size.

Thanks in advance

This is what you have so far:

your smclk clock is ticking away at 1mhz
Getting 50KHz cycle rang: 1'000'000/50'000= 20  (-1 for CCR0)

You can only use whole numbers for ccr1 and ccr2, as of course there is no decimal point
You only have 0-19 numbers as your options to use = 5%,10%,15%,20%,25%........................... duty

If that is not acceptable:

1: go with 10KHz cycle (if OK) 1'000'000/10'000= 100 (-1 for CCR0)
   and you now have 0-99 range for ccr1 and ccr2 = 1 % steps

2: go with 8MHz SMLK, 8'000'000/50'000= 160  (-1 for CCR0) 
    and you now have 0-159 range for ccr1 and ccr2 = 0.625 % steps

Prakash Balagangatharan said:

so if i am not getting step size as1 like as 2 or 0.4 or some other values means i can't able to get the exact duty cycle value am i write? pls clarify.

Read carefully what I have written 10 times and use a calculator to calculate what you are doing.

Prakash Balagangatharan said:

Also if look into the frequency that also varies not the given one Why? Is this also has any dependent like step size.

As clock source for your timer you have selected ACLK, this is default connected to an XTAL, do you have one?

After boot you have to wait a short time until all clock sources are stable.

Prakash Balagangatharan said:

so if i am not getting step size as1 like as 2 or 0.4 or some other values means i can't able to get the exact duty cycle value am i write?

You shall realize that CCR1 is not "PWM duty setting register", it is compare register. In your case timer counts from 0 to 19, so compare (CCR1) register shall be within this range too. Obviously you can't get 1% (step) resolution of PWM if you have just 20 useable values for CCR1 which controls duty cycle!

Increase timer period, CCR0

Ilmars said:

Increase timer period, CCR0

so if i want to get a duty cycle is not a multiple of timer ticks i can able to get only the nearest multiples values of the timer tics.

 but if you see my attached file why first 3 cycle i am not getting the expected frequency and duty cycle. After that also the frequency i am getting is slightly varied.

can any one explain why is it like

Thanks in advance

Maybe because you are using ACLK clock to source TimerA0, and ACLK <> 1MHz?

TASSEL_1           /* Timer A clock source select: 1 - ACLK  */
TASSEL_2           /* Timer A clock source select: 2 - SMCLK */

There is no duty register, we just call the result that.

Say due to time limit can only use 20 lego blocks as the cycle Freq
You now have to decide what blocks # 0-19 that should be set high and the rest will then be low.
As CCR1 register (result is the duty) is just the same as CCR0 when it comes to compare a match to the TA0R Counter

Prakash Balagangatharan said:

so if i want to get a duty cycle is not a multiple of timer ticks i can able to get only the nearest multiples values of the timer tics.

To get 87% duty cycle with absolute precision you would need PWM period to be equal 100 and PWM match register to be 87. Good choice would be 23 and 20 either, then you shall use 1.15 MHz timer clock to get 50kHz PWM freq.

Prakash Balagangatharan said:

also the frequency i am getting is slightly varied.

Indeed. Because you use DCO oscillator which is giving average of two frequencies. Please search this forum for further information about how DCO works and why it is not "perfect source of the clock or frequency"