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Cannot make xmit service ISR

Dubs Mozz
Intellectual 330 points

Other Parts Discussed in Thread: MSP430F5659

Hello

I'm working with a msp430f5659 with a UART that is working well -   type a series of characters which trigger receiver interrupt which fills up a receiver buffer.   Life is good.  So I copy the receiver buffer into a xmit buffer and 

so I disable xmit interrupts

  UCA1IE &=  ~UCTXIE;

fill the xmit buffer 

then set the xmit flag 

 UCA1IFG |= UCTXIFG;

re-enable xmit interrupts 

 UCA1IE |= UCTXIE;

and....nothing.   I step through it and sure enough, the enable is 0, then buffer is filled, then I enable the interrupt, I see it go to 1, flag is a 1, and as I step through the program just continues along as though there is no xmit interrupt pending.

what am I missing?  with my old 8051 I would just fill my buffer, set TI = 1, and there you go, next instruction execution would jump to the xmit  ISR.  My ISR will empty the buffer into UCA1TXBUF but the problem i'm having is how do I enable the xmit ISR?   I have one routine, it tests

switch(__even_in_range(UCA1IV,4))

and when I write to the receiver buffer, it does jump to the ISR and UCA1V = 2, but never jumps for a xmit flag, never jumps in with UCA1V =  4. 

Any ideas what I'm doing wrong?

Thank you in advance for your help

Dubs

  • 0
    Guru 12050 points

    Did you set up &P1SEL and &P1SEL2 for tx-pin too?

    Did you put a breakpoint inside various part inside IRQ to see if it get serviced at all?

    >then set the xmit flag > re-enable xmit interrupts 

    I only use xmit interrupt as on/off, as the last byte sent sets IFG flag when that bytes gets moved to output stage.
    So just have the IRQ turn off its own xmit interrupt when last byte is sent.

    At boot-up clear tx_bit in IE2  and set IFG (on USI in SPI mode dummy write a 0, as first byte may be 9 clocks)
    after I fill the buffer and reset a pnt to first char, I enable tx-bit in IE2.
    The ISR then checks if this was the last char to transmit and clear tx_bit in IE2 on exit.
    IFG is pretty much always set and is never used by the code, just a way for the ISR to control its own flow.

  • 0
    TI__Guru 56650 points

    Hi,

    when you said transmit buffer, do you mean it is a software(SRAM) buffer or the hardware transmit buffer UCTXBUF? You need to manually pass the data to the hardware transmit buffer UCTXBUF so the data get sent out.

    Please refer to the example codes: http://www.ti.com/lit/zip/slac539

  • 0
    Guru 227245 points

    The approach that worked best for me so far is:

    ISR checks TXIFG bit (NOT using IV register, as this would clear the bit!). If set, check whether there is data to send. If so, write to TXBUF (which will clear the TXIFG bit). If not, it clears the TXIE bit(!), so no further interrupts.

    Main writes data to buffer (with GIE clear) and then sets TXIE bit (whether clear or not) This will kick the TX interrupt again. The TXIFG bit is only read and never manually cleared or set.

    The buffer is implemented as 256 bytes ring buffer. Same for RX.

    Works like a charm for 4 UART lines on 115200Bd simultaneously. :)

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