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UART Mode High Baud Rate Errors

Tom Cannon
Prodigy 180 points


I found a solution and want to share it.  I am using a MSP4305419A USI in the UART mode with  'desired' baud rate of 460,800 bps  (7-data, 1-stop, no parity)  

Sending packets of 32 bytes I was experiencing errors once every few thousand packets.  Multiple receiver devices all pointed to the MSP transmit as the BAD guy.  

At ~25Mhz MCLK  (DCO @ 762 multiplier off low freq 32,768Hz crysta)l and SMCK  at divide by 1 the baud rate generator required MODULATION.  The modulation and bit error is the apparent problem.


The solution was to pick a DCO multiplier that set the MCLK to a frequency that is VERY close to integer multiple of 460,800Hz.    

Crystal freq of 32,768 Hz * 731 = 23,953,408 Hz (MCLK)

 23,953,408 Hz / 52  = 460,642   Baud Rate Error of 0.034%

The MCLK and CPU run at 23.9 Mhz (below the faster 25Mhz possible) but with no UART data errors.

Perhaps there is a frequency closer to 25 Mhz that will produce no errors with modulation but I can live with 23.9 Mhz CPU speed.

  • 0
    TI__Guru 56650 points

    Tom,

    thanks for sharing. I also think that the flexibility of the UCS module can bring a lot of advantages to many applications such as yours.

  • 0
    Guru 227245 points

    Tom, running the MSP with 25MHZ from DCO is not recommended anyway. DCO output frequency is an average of slower and faster clock cycles. And the faster ones will exceed 25MHz, violating the specs.
    For UART, there is the modulation. It tries to keep the error small when the baudrate is a non-integral fraction of the clock. However, this error (can be found in the users guide) adds to the clock error.

    Keep in mind that the DCO can only produce a limited number of unique frequencies (which are also drifting). The FLL is not a PLL. It only adjusts the DCO up or down if it is too slow or too fast. So the resulting frequency is only a long-time average. For individual bits, especially on a small divider, the individual bit rate error might be quite large, even though the average baudrate is next to perfect.

  • 0 in reply to Jens-Michael Gross
    Prodigy 180 points

    Good to know about the DCO.  This is probably why I was getting errors only very seldom.  If I do not run the MCLK via the DCO as a multiple of the 32,768 low freq crystal, how do you recommend setting the MCLK freq??  (Hi freq xtal??)

    Thanks

  • 0 in reply to Tom Cannon
    Guru 227245 points

    A crystal is always the best option for an (almost) clean, precise, stable, jitter-free clock.

    You can reduce the DCO jitter by running it at a multiple (x2 or x4 through FLLD) and use DCOCLKDIV as source for SMCLK. This will reduce the jitter due to modulation. It won’t, however, reduce the other errors.

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