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Frequency accuracy and calibration frequency

asher bara
Intellectual 900 points


Hello ,

I working on the 430f5438a. The processor should work at a frequency of 16mhz ,  and I'm considering whether it is necessary calibration frequency operation.

I write code based on the component's internal frequency (REFO) and after passing through the frequency stabilization (FLL).
In order to know whether there is a need calibration frequency operation, the question arises what is the frequency accuracy of the component without frequency stabilization action?

According to the literature of the component : datasheet (slas655d.pdf, page 51) , the accurracy of the REFO in the worst case (over recommended ranges of operating free-air temperature) the accuracy is +/-3.5%.

The missing data to calculate the accuracy of the component is what is the accuracy  of the DCO.  In the  literature (slau208n.pdf , user guide) the  accuracy blocked by 8%. . But it does not say what exactly.

Page 162: “The five DCO bits divide the DCO range selected by the DCORSEL bits into 32 frequency steps, separated by approximately 8%”  

So my questions:

  1. What is the excatly the accuracy of the DCO? .  
  2. how can I calculate the accuracy of the MCLK  (while the MCKL is based on the  REFO using the DCO) .
  3. And how affect the FLL on the frequency accuracy?

 

Thanks.

 

 

  • 0
    Guru 227245 points

    You’re right about the REFO tolerance. However, at a given VCC/temp, the frequency is quite stable, yet the exact value is unknown.
    Now for the DCO. It is a free-running R/C oscillator where R and C can be digitally switched. A certain R and C combination produces a DCO frequency whose range is listed in the datasheet.
    To go beyond the limited number of frequencies available with the limited number of R and C, the DCO can use modulation. Which means it constantly switches between Cn and Cn+1, depending on the modulation pattern. After a full pattern (32 clock cycles) you have an average(!) frequency that is much closer to your desired result. However, it is likely not a perfect match. Now the FLL compares the number of clock ticks during one reference period with the configured factor. And adjusts the modulation pattern one step up or down, or switches to Cn+1 with no modulation or Cn-1 with max modulation.

    So you have
    - the inability of the DCO to produce the desired frequency exactly.
    - the jitter from DCO modulation (short-term jitter)
    - the jitter caused by FLL adjustment (long-term jitter)
    - the frequency error of REFO

    Over a longer period of time, the frequency error almost completely depends on REFO. But for each individual clock pulse, the error can be additional ~8% due to DCO frequency quantization. Unless the rare case of the DCO coincidentally producing exactly the desired frequency.
    So expect a frequency error of up to 12% for individual clock cycles.

    You can smoothen this a bit by running the DCD with a multiple of the target frequency and use the FLL input divider (and DCOCLKDIV). In this case you’ll reduce the short-time jitter to 0 for not only modulation 0 but also modulation = 50% (and on factor 4 also for 25% and 75% modulation) and ease it for all other cases.

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