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UART connection problem on MSP430F5529 LP

Other Parts Discussed in Thread: MSP430F5529, MAX3232

HI there,

We are trying to communicate data on UART. At first, we took example code from CCS for msp430f5529 (project name :  "MSP430F55xx_uscia0_uart_04").This will echo data recieved at UART (baud 9600).

Launch Pad jumpers are connected as shown in the following picture.

1. We have opened Putty and configured it with same baudrate and 8bit data with one stop bit.

2. Connected Programmed LP to USB port of Laptop.

3. When we are trying to type charaters are Putty it is not echoing them. We tried with Hyper terminal also, but still the same problem.

4. Is there any connection on LP that we are missing ?

following is the code for it.:

#include <msp430.h>

int main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
P3SEL = BIT3+BIT4; // P3.4,5 = USCI_A0 TXD/RXD
UCA0CTL1 |= UCSWRST; // **Put state machine in reset**
UCA0CTL1 |= UCSSEL_2; // SMCLK
UCA0BR0 = 6; // 1MHz 9600 (see User's Guide)
UCA0BR1 = 0; // 1MHz 9600
UCA0MCTL = UCBRS_0 + UCBRF_13 + UCOS16; // Modln UCBRSx=0, UCBRFx=0,
// over sampling
UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
UCA0IE |= UCRXIE; // Enable USCI_A0 RX interrupt

__bis_SR_register(LPM0_bits + GIE); // Enter LPM0, interrupts enabled
__no_operation(); // For debugger
}

// Echo back RXed character, confirm TX buffer is ready first
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=USCI_A0_VECTOR
__interrupt void USCI_A0_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(USCI_A0_VECTOR))) USCI_A0_ISR (void)
#else
#error Compiler not supported!
#endif
{
switch(__even_in_range(UCA0IV,4))
{
case 0:break; // Vector 0 - no interrupt
case 2: // Vector 2 - RXIFG
while (!(UCA0IFG&UCTXIFG)); // USCI_A0 TX buffer ready?
UCA0TXBUF = UCA0RXBUF; // TX -> RXed character
break;
case 4:break; // Vector 4 - TXIFG
default: break;
}
}

  • Hi,

    referring to the User's Guide document:

    http://www.ti.com/lit/ug/slau533b/slau533b.pdf

    chapter 2.2.6 Application (or "Backchannel") UART, the UART backchannel is connected to USCI_A1 UART which are P4.5 and P4.4 (see chapter 6 "Schematics")

    In your code, you are using USCI_A1 with P3.4 and P3.5.

  • Hi Leo Hendrawan,

    Thank you for your information. Now it is working.

  • After establishing communication over UART (UCA0) with Beagle Bone Black at baud rate of 9600,

    We are trying to make this communication happen at faster rate.

    wanted to increase baud to its maximum 460800. As an intermediate step we are increasing it to 115200, and then to 230400. Please find commented part showing settings for these baud rates. 

    1. Clock source chosen  is SMCLK (running at 8MHz).

         When I scoped this clock on pin 2.2, SMCLK is observed to be varying from 7.947 MHz to 8.469 MHz.

         Will this affect baud rate or robustness of data reading ? because for same baud rate UCBRx values are different for 8.0 MHz and 8.388 MHz.  

    2.  No oversampling enabled.

    3. Modulation types are as per TI guidelines.

    4. UCA0BR0 and UCA0BR1 values are as per TI guidelines.

    CODE :

     

    #define BAUD_460800_WITH_SMCLK_8M 17

    #define BAUD_230400_WITH_SMCLK_8M 34
    #define BAUD_115200_WITH_SMCLK_8M 69
    #define BAUD_9600_WITH_SMCLK_8M     873   // also tried with 768 as per one of the TI E2E discussion

    /************************************************************************************/

    void Uart_HW_init(uint8_t baudrate, uint8_t options)
    {

        P3SEL |= BIT3+BIT4;                               // P4.4,5 = USCI_A0 TXD/RXD
        UCA0CTL1 |= UCSWRST;                      // **Put state machine in reset**
        UCA0CTL1 |= UCSSEL__SMCLK;       // SMCLK. 8 MHz clock source

        // //setting baud rate of 460800 with smclk = 8 MHz
        // UCA0BR0 = BAUD_460800_WITH_SMCLK_8M; //
        // UCA0BR1 = 0;
        // UCA0MCTL |= UCBRS_3 + UCBRF_0 + UCOS16; // Modulation UCBRSx=3, UCBRFx=0, oversampling = No

        // //setting baud rate of 230400 with smclk = 8 MHz
        // UCA0BR0 = BAUD_230400_WITH_SMCLK_8M; //
        // UCA0BR1 = 0;
        // UCA0MCTL |= UCBRS_6 + UCBRF_0 ; // Modulation UCBRSx=6, UCBRFx=0, oversampling = No

        //setting baud rate of 115200 with smclk = 8 MHz
        UCA0BR0 = BAUD_115200_WITH_SMCLK_8M; 
        UCA0BR1 = 0;
        UCA0MCTL |= UCBRS_4 + UCBRF_0 ; // Modulation UCBRSx=4, UCBRFx=0, oversampling = No

        // //setting baud rate of 9600 with smclk = 8 MHz
        // UCA0BR0 = BAUD_9600_WITH_SMCLK_8M - ((BAUD_9600_WITH_SMCLK_8M >> 8) << 8);
        // UCA0BR1 = BAUD_9600_WITH_SMCLK_8M >> 8;
        // UCA0MCTL |= UCBRS_7 + UCBRF_0; // Modulation UCBRSx=0, UCBRFx=0, oversampling = No 

        UCA0CTL1 &= ~UCSWRST; // Initialize USCI state machine
        UCA0IE |= (UCRXIE); // Enable USCI_A0 RX interrupt

    }

    We are not able to communicate with baud rates 115200 or more.,

    Can you please help us to find where we are going wrong. 

    Thanks and Regards,

    Bharat G

  • Bharat, this question is not related to the original topic of the thread, so you should have started your own thread with an appropriate thread title.

    However...

    It seems you’re using 4x or 5x/6x family device and an FLL-stabilized DCO as clock source. The DCO only has a limited number of different output frequencies. So to get the target frequency you want, it switched between two available frequencies above and below the target, based on a modulation pattern. So of ever 32 clock cycles, some are slower and some are faster than wanted, in average coming as close to the target frequency as possible. But if you look at each individual clock pulse, they will significantly differ. And values will be different for different MSPs too.
    Also, by default, the FLL runs with the internal REFO as reference, which has ~2% error. This adds to the average frequency error.
    If you want a more precise SMCLK, either add an external 32768Ht reference quartz (eliminates the REFO error) or use a real 8Mhz crystal (gives nearly jitter-free 8MHz).

    When using the DCO as clock source for the USCI, DCO clock speed and baudrate have to be considered. If the baudrate divider (UCBRx) is >32, then the DCO jitter is unimportant. Just assume the average frequency of the DCO.

    For 460600Bd, the divider is only 17, so depending on the actual modulation pattern, an additional error is added to two adjacent bits, in addition to the error introduced by the non-integral divider (compensated in average by USCI baudrate divider modulation). But even with exact 8MHz, the maximum bit time error is already >5%.
    I suggest going for 16MHz DCO clock speed. For MCLK, you can then use a /2 divider if you want to run it with 8Mhz.

    However, you shouldn’t have problems communicating with 115200Bd at all.

    Perhaps you should post your clock system setup.

  • Thank You Jens-Michael Gross,

    Followings are information of my MSP430 board.

    1. MSP430 series -> MSP430F5529.

    2. I have attached 32768 Hz crystal to XT1.

    3. DCO now increased to 20 MHz. Please find the code for clock setting.

    4. XT1 CLK crystal is used as reference for DCO (FLLREFCLK). And as you mentioned even with this setup still I can see 5% error in DCO output.

    5. Now this DCO is used as clock source for UART module. This ensures that UART divider value is always greater than 32 and it will keep away from jitter problems due to averaging.


    6. I still facing problem in communication.

    7. Please look into following code. If everything is correct with the settings then I need to work on the way I handling Packet (Bunch of Bytes after they arrive).

    Please do correct me if I am wrong in setting any part of it.

    System Clock Setting code :

    void System_Init( void )
    {

    ////-------------------CLOCK------------------------------------------------
    //// ACLK = 32kHz, MCLK = SMCLK = 20MHz
    ////
    P5SEL |= BIT4 + BIT5;;                 // Select XT1
    UCSCTL6 &= ~(XT1DRIVE_0);    // Max drive on XTAL
    UCSCTL6 |= XCAP_3;                  // Internal load cap. 6pF, enough?

    // Loop until XT1,XT2 & DCO fault flag is cleared
    do
    {
    UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);  // bit XT1HFOFFG of register UCSCTL7 is not available in MSP430F5529
                                                                                                     // Clear XT2,XT1,DCO fault flags
    SFRIFG1 &= ~OFIFG;                                                           // Clear fault flags
    } while (SFRIFG1&OFIFG);                                                   // Test oscillator fault flag
    UCSCTL6 &= ~(XT1DRIVE_3);                                            // Xtal is now stable, reduce drive strength

    UCSCTL0 = 0x0000;                                                              // Set lowest possible DCOx, MODx
    UCSCTL1 = DCORSEL_6;                                                    // Select DCO range 16MHz operation
    UCSCTL2 = 610;

    UCSCTL4 = SELA__XT1CLK | SELS__DCOCLK | SELM__DCOCLK ;              // use 32k xtal

    P2SEL |= BIT2 ;                                                                     //for debug; to scope SMCLK clock and check stability.
    __no_operation();

    }

    UART initialization code :

    void Uart_HW_init(uint8_t baudrate, uint8_t options)
    {
      P3SEL |= BIT3+BIT4; // P4.4,5 = USCI_A0 TXD/RXD
      UCA0CTL1 |= UCSWRST; // **Put state machine in reset**
      UCA0CTL1 |= UCSSEL__SMCLK; // SMCLK
      UCA0BR0 = 173; // 115200 Baud
      UCA0BR1 = 0;
      UCA0MCTL |= UCBRS_5 + UCBRF_0; // Modulation UCBRSx=5, UCBRFx=0
      UCA0CTL1 &= ~UCSWRST; // Initialize USCI state machine
      UCA0IE |= (UCRXIE); // Enable USCI_A0 RX interrupt
      tx_iptr = 0;
      tx_optr = 0;
    }

    UART Service routine :

    #pragma vector=USCI_A0_VECTOR
    __interrupt void USCI_A0_ISR(void)
    {
      switch (__even_in_range (UCA0IV, 4))
      {
        // Vector 0 - no interrupt
        case 0 :
        break;

        // Vector 2 - RXIFG
        case 2 :
        if(_RxEventHandle!=NULL)
       {
          _RxEventHandle(UCA0RXBUF);
        }
        LPM3_EXIT;
        break;

        // Vector 4 - TXIFG
        case 4 :
        if (tx_iptr != tx_optr)
        {
          UCA0TXBUF = tx_buf[tx_optr];
          tx_optr++;
          tx_optr &= (SERIAL_TX_MAX_LEN-1);
          if (tx_optr == tx_iptr)
          {
            UCA0IE &= ~UCTXIE; // Disable USCI_A0 TX interrupt
            tx_iptr = 0;
            tx_optr = 0;
          }
      }
      break;

      default :
      break;
    }
    }

    Thank You and Best Regards,

    Bharat Gebise

  • For MCLK >8MHz, you’ll need to raise PMMCOREV. Else the CPU hasn’t enough voltage to run and anything can happen.

    Whether the internal capacitors are suitable for your crystal depends on the crystal you use. Only you can know.

  • Dear can you please the code for receiving the char from hyper terminal. I facing problem while receiving.
    I am using following code for receiving

    char vgetchar()
    {
    while (!(UCA1IFG & UCRXIFG));
    return UCA1RXBUF;
    }

    But I didn't get any char value
  • For receiving (and waiting for data to come in), this code should do. However, you need to configure the USCI before it even starts listening on the line. It only needs to be done once, but it needs to be done and needs to be done correctly (including port pin configuration and baudrate calculation).
    Also, keep in mind that the USCI signals are TTL-level while a PC COM port (and most USB/SER converters) use RS232/V.24 signal levels which my fry the MSP port pins. You'll need a converter such as the MAX3232 in this case.
  • Your sample code says its using UARTA0, when we changed to A1, the program is working fine. 

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