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MSP430F5438 SPI Questions

Oscar Palomino
Intellectual 780 points
Other Parts Discussed in Thread: MSP430F5438

Hi Team,

A customer has some questions on the MSP430F5438:

1.       The MSP430 is configured as a SPI master. When doing a multi-byte transfer using DMA what is the maximum intra-byte delay time seen on spi bus pins?

(I’ve looked at the pins using an o’scope and I do not see a measurable delay.)

2.       On page 56 of MSP430F5438:

1.       What are the SPI timing values (tsu, thd, etc)  when the voltage level is 3.3V (Datasheet only specifies 2.5 & 3V) ?

2.       On that same page why is there an additional data bits seen on the SIMO lines (after the final SPI clk bit)?

3.       On the same page is UCLK equivalent to UCxCLK for the spi peripheral?

 Your help is much appreciated!  Thanks.

 

Regards,

Oscar

 

 

  • 0
    TI__Mastermind 26380 points

    Hello,

    Oscar Palomino said:
    1.       The MSP430 is configured as a SPI master. When doing a multi-byte transfer using DMA what is the maximum intra-byte delay time seen on spi bus pins?

    The SPI transmit and receive buffers are double buffered. Hence the module itself is capable of back-to-back transfers with no delay in between. The only overhead between bytes is attributed to data hadling in the application code.

    Oscar Palomino said:
         What are the SPI timing values (tsu, thd, etc)  when the voltage level is 3.3V (Datasheet only specifies 2.5 & 3V) ?

    We are trying to spec these parameters for various Vcore levels in the future. For now you can still use the 3.0V data for ballpark guidance.

    Oscar Palomino said:
      On that same page why is there an additional data bits seen on the SIMO lines (after the final SPI clk bit)?

    Are you referring to Figure 12 on the page 57? The diagram is simply showing the difference between CKPL=1 or 0. If you are looking for a more detailed timing diagram check out Figure 20-4 in the 5xx Family User's Guide.

    Oscar Palomino said:
      On the same page is UCLK equivalent to UCxCLK for the spi peripheral?

    Yes.

    Regards,

    Priya

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