unfair Cortex M0/MSP430 energy benchmark comparison

But still, aren't they comparing a Freescale ARM superior to that MSP430 compared? They don't relay give that much info about the MCUs compared, i doesn't show performance comparisson or number of peripherals.

I would like to see them compara it with a FRAM, that would surely beat the it in power efficiency and even maybe inperformance

I have lots of MCUs that do not consume any energy ;-)

I do not even need to write code, they automatically go to very deep sleep!

that's amazing! :p

More detailed description / comparison, not only regarding consumption...

http://forum.43oh.com/topic/3416-stm32l-vs-msp430f5-whats-left-for-msp430

The trick with getting a good (for you) comparison is to pick operating conditions that are good for you and bad for the competition.

The CoreMark code doesn’t make any use of low power functions, core voltage settings etc. So if you leave everything at default, things are bad for the competitor. But of course on your own system, you do all necessary configurations.
You can pick the compiler of choice. So pick the best one for you and the worst one for the competition.
As long as you document in a footnote what you’ve done, the comparison is legally valid even though it doesn’t say much.

 For example: the used MSP430F5529 could run on 3.6V but they run it on 3.3V. This means that the internal voltage regulator needs to draw more current, even though it consumes the same energy.
Running the MSP on lower frequency would allow it to run on lower core voltage with lower current consumption/MHz. The ARM likely scales linearly with core clock.

 Surely, the comparison does not count just for core current, but also for the peripherals (which aren’t there on the ARM)

 I don’t know the CoreMark well. I don’t know whether it might use floating point math or 32bit operations, on which the ARM would have some advantage.

 They used CCS instead of IAR (which gives better results when optimizing for speed)

 Using better conditions and an IAR CoreMark value posted on the EEMBC website, I can calculate a value of 3.1. And when running from ram instead of flash, it goes up to 5.5. This is with 3.0V supply. On 3.6V it would be even higher.
And the 5438A has about 10% less core current@25MHz.

But I’d like to see how low (in absolute operating current) the Kinetis can go if it is not running on 48MHz. Likely, its performance goes dramatically down then.

 In a different thread, I could achieve a gain of +20% on the Dhrystone benchmark speed by using a generic (not optimized byte transfer) DMA transfer function in replacement of the standard memcpy. Since I knew the source code, I could have optimized it further and maybe doubled the gain (by using word transfers, knowing of the alignment).

All:

This white paper talks in lengths about standby power consumption and intelligent peripherals. As Jean-Michael Gross mentioned, CoreMark is designed to benchmark CPU performance and there is no standby power usage in the code/benchmark. The paper indicates that they modified the CoreMark code in which they made it sleep for 5-seconds in an equivalent LPMx.5 mode after executing the CoreMark. Though I would argue that you should not be modifying the CoreMark for its intended purposes. And plus they used the MSP430F5529 which is not as low power as the MSP430FR5969.

Now, the better benchmark that EEMBC just released to benchmark Low-Power MCU is ULPBench. This benchmark was created as part of a working group from various MCU vendors across the industry to benchmark low-power MCUs in an even playing field. And this benchmark simulates a typical low-power application where it periodically wakes-up every second to perform a task and re-enters LPM.

Regards,

William