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MSP430F2272 watchdog question.

Doug Baker
Genius 3420 points

Other Parts Discussed in Thread: MSP430F2272

I am running a MSP430F2272 CPU using CCS 5.3.  I have a question about the watchdog. 

I have the clocks set up as follows:

MCLK = 8MHz (can’t confirm by scope, this is clock not supported for hardware debug on this CPU)

SMCLK = 2MHz (confirmed by scope using CPU pin to show the clock externally)

ACLK = 32kHz 2MHz (confirmed by scope using CPU pin to show the clock externally)

My question is about the watchdog timeout if in the watchdog control register the WDTIS bit has any effect for watchdog operation.

I was thinking that if the ACLK is 32768Hz, and I set the watchdog register WDTCTL to  WDTPW + WDTCNTCL + WDTSSEL;  the clock would be divided by 32768 due to the WDTIS field in the WDCTRL register.  With the settings as described above where (ACLK=32kHz) and (WDTCTL = WDTPW + WDTCNTCL + WDTSSEL), the watchdog times out almost instantly as far as I can tell in the debugger.  I assume the timeout is really 1 second and that that field WDTIS has no effect in watchdog mode.  I am referencing the document SLAU144l Jan 1012 and the watchdog is described in Ch10.   Is that assumption correct that the WDTIS field has no effect in watchdog mode? Based on my settings, what is the expected watchdog timeout?

Thanks,

Doug

  • 0
    Guru 25210 points

    Doug Baker said:
     Is that assumption correct that the WDTIS field has no effect in watchdog mode?

    No. The documentation for those bits specifically says "... and/or generate a PUC." which means they apply in watchdog mode.

    Doug Baker said:
    Based on my settings, what is the expected watchdog timeout?

    1 second. (32768 count / 32768 Hz frequency = 1 second time period.)

    Doug Baker said:
    I am referencing the document SLAU144l Jan 1012

    The latest revision for this document is "J", July 2013 (http://www.ti.com/lit/pdf/slau144)

  • 0 in reply to Brian Boorman
    Genius 3420 points

    I see that looking at the include file for the chip, it has the folowing that has a few "examples". 

    Thanks for the help!

    From msp430f2272.h:

    /* WDT is clocked by fACLK (assumed 32KHz) */
    #define WDT_ADLY_1000       (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL)                 /* 1000ms  " */
    #define WDT_ADLY_250        (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0)          /* 250ms   " */
    #define WDT_ADLY_16         (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1)          /* 16ms    " */
    #define WDT_ADLY_1_9        (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0)   /* 1.9ms   " */

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