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How to set Watch dog timer

Ashutosh Pailwan1
Expert 2480 points
Other Parts Discussed in Thread: MSP430G2553

I am using MSP430G2553

The clk source is external crystal of 32678 Hz

Watchdog is clked by ACLK clk which sourced by external crystal

By below code after how much time interval watchdog will reset the CPU

WDTCTL = WDTPW + WDTHOLD; // stop watchdog timer

  WDTCTL = WDTPW + WDTSSEL + WDTIS0 + WDTIS1; // TIMER COUNTER =CLK SOURCE/64 clk SOURCE

As I am confusd since the WDTCTL register WDTSIx bits what it actually does

it says watchdog clock source/64 means what.

  • 0
    Guru 25210 points

    Ashutosh Pailwan1 said:
    As I am confusd since the WDTCTL register WDTSIx bits what it actually does

    These bits determine what the "terminal count" value is that is used to generate a watchdog reset.

    So:

    • WDTSSEL -> Selects ACLK
    • WDTIS0+WDTIS1 -> Selects /64

    You specified that your ACLK is from XT1 which is 32768 Hz.

    Your WDT will fire a reset after 64 ACLK cycles. This is (64/32768) seconds = 1.953 milliseconds.

    In other words, unless you "feed the dog" it will "bite you" (i.e. reset the micro) after 1.953 milliseconds.

  • 0 in reply to Brian Boorman
    Expert 2480 points

    I thought my counter value will be 32768/64  i.e after counter value will be 512 . So my watchdog will fire after 512 /32678 =15.625 msec

    Ok if you are correct I want to reset watchdog after 1.07 sec howz it possible.

    I am using timer interrupt of 1 sec which is sourced by external oscillator with counter value 4096. I want to service watchdog in timer interrupt programm i.e after 1.07 sec

  • 0 in reply to Ashutosh Pailwan1
    Guru 25210 points

    Ashutosh Pailwan1 said:
    I thought my counter value will be 32768/64

    You should study the peripheral block diagram in the 2xx User's Guide (it's Figure 10-1). The WDTIS bits select which tap of the counter is used to generate the reset pulse.

    Ashutosh Pailwan1 said:
    I want to reset watchdog after 1.07 sec howz it possible.

    You need a slower clock. The best you can do now is 32768Hz/32768 = 1.0 seconds (setting WDTIS[] = "00").

  • 0 in reply to Brian Boorman
    Expert 2480 points

    Dear Sir,

    1. I am refering MSP430G user guide but it is not clear to understand.

    2. In previous thread u said the counter will reset by 64/32768hz i.e 15.2 msec, if clock source is external oscillator of 32678 hz and counter setting is WDTIS0 + WDTIS1

    3. Now u are saying if we set WDTIS0 we can achive  1sec timer reset interval as 32678hz/32768

    4. Which is correct one i.e counter division value / clk source frequency or  clock source frequnecy/ counter division value.

    5. I am confused as the clock source/ factor. The factor is counter value itself or divsion factor of clcok frequecny.

    6. If I want to achive timer value more than 1 sec what should I do , as I am confused please elaborate

  • 0 in reply to Ashutosh Pailwan1
    Guru 25210 points

    Ashutosh Pailwan1 said:
    2. In previous thread u said the counter will reset by 64/32768hz i.e 15.2 msec, if clock source is external oscillator of 32678 hz and counter setting is WDTIS0 + WDTIS1

    No I didn't. I said it would fire after 64 ACLK cycles. You said your ACLK is 32768 Hz. That is 1.953 msec,

    Ashutosh Pailwan1 said:
    3. Now u are saying if we set WDTIS0 we can achive  1sec timer reset interval as 32678hz/32768

    No I didn't. I said if you make both WDTIS0 and WDTIS1 a logic '0' (i.e. WDTIS[] = "00") then you can achieve a 1-second time on the WDT.

    Ashutosh Pailwan1 said:
    4. Which is correct one i.e counter division value / clk source frequency or  clock source frequnecy/ counter division value.

    They are both correct. Only difference is the units. In one case I specified the result in milliseconds, the other case I wrote it as 1 Hz which equals 1 second if you take the reciprocal.

    Ashutosh Pailwan1 said:
    5. I am confused as the clock source/ factor. The factor is counter value itself or divsion factor of clcok frequecny.

    The WDTIS bits control which tap of the counter is used to generate the reset pulse. Looking at the diagram you can see they select which tap makes it through the mux block.

    Ashutosh Pailwan1 said:
    6. If I want to achive timer value more than 1 sec what should I do , as I am confused please elaborate

    Since 32768 is the maximum value the counter can count to, you would need a clock slower than 32768 Hz. I already told you that.

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