Comparator A+ outputs high when switched off if CAF is set

The MSP430x2xx family user guide has a block diagram of Comparator A+, part of which is shown below:

This suggests that when CAON is clear the comparator is unpowered and the AND gate after the comparator is forced to output zero. Section 21.2.1 confirms this, saying: "When the comparator is switched off, the CAOUT is always low" (although that's incorrect if CAEX is set). This all works as expected as long as the CAF bit in CACTL2 is clear.

According to the diagram setting CAF just enables an extra filter on the output to minimise oscillation. What I've found is that setting CAF while the comparator is disabled actually forces CAOUT high. It also results in CAIFG becoming set if the comparator is configured to interrupt on the rising edge.

Here's some code that demonstrates the problem:

/* Test of CA+ CAF
 * Jumper P1.5 (toggled GPIO output) to P1.4 (A4 input)
 * Connect P1.1 to a scope to see reference voltage
 * Connect P1.7 to a scope to see CAOUT
 */

#include <msp430.h>

void test_comparator();

void main()
{
    WDTCTL = WDTPW | WDTHOLD;

    CAPD = BIT1 | BIT4;		// Disable digital input on P1.1 and P1.4 to avoid cross current
    P1DIR = 0xFF;
    P1OUT = 0;
    P1SEL = BIT7;			// Select CAOUT output for P1.7

    CACTL1 = CAREF_2;		// Set reference voltage to 0.5VCC
    CACTL2 = P2CA4 | P2CA3;	// Select CA1 for non-inverting input and CA4 for inverting input

    test_comparator();		// Test without output filter

    CACTL2 |= CAF;			// enable output filter

    test_comparator();		// Repeat test with output filter

    __bis_SR_register(LPM4_bits);
}

#define __debugbreak() __op_code(0x4343)

void test_comparator()
{
    P1OUT |= BIT5;			// Output high on P1.5 (jumpered to P1.4) to ensure comparator outputs low as soon as it is enabled
    __debugbreak(); 		// Break and check scope: CAOUT should be low as the comparator is disabled.

    CACTL1 |= CAON;			// Enable comparator
    __debugbreak();			// Break and check scope: CAOUT should be low as the inverting input is at VCC and non-inverting input is at 0.5VCC

    P1OUT &= ~BIT5;			// Take P1.5 (and P1.4) low
    __debugbreak(); 		// Break and check scope: CAOUT should be high as the inverting input is at GND and non-inverting input is at 0.5VCC

    CACTL1 &= ~(CAON | CAIFG);
}

On the first run through test_comparator() the output will match the descriptions on the breakpoint lines. On the second run CAOUT will be high on the first breakpoint line - in fact it goes high as soon as the CAF bit is set in main. When the comparator is actually enabled the output drops low as expected.

This issue has been observed on MSP430G2553 and MSP430G2452. I've also tried the equivalent code on Comparator B (MSP430F5529), which doesn't suffer from this issue.

To work around this you can ensure CAF is not set until after CAON is set, and clear CAF before clearing CAON. Alternatively you can ensure your code doesn't depend on the states of CAOUT, CAIFG and CCI1B at any time that CAON is not set.