Other Parts Discussed in Thread: MSP430F2132
We use an MSP430F2132 in two different assemblies. The firmware for the two boards is different but they use the same clock settings and baud rate. In both assemblies we are seeing batches of processor that will not communicate correctly. When debugging the firmware it was found that the factory calibrated DCO settings that are stored in flash do not generate an accurate clock. Below is the code we use to set a 1 MHz clock and 9600 baud rate (UCAXBR divider of 104 according to processor specs 1 MHz / 9600).
// this adjusts the DCO's fundemental frequency
BCSCTL1 = CALBC1_1MHZ; // Set DCO
DCOCTL = CALDCO_1MHZ;
// initialize UART to 9600 baud based on 1 MHz clock / 9600 = 104 (0x68) remainder 1
UINT8 tbuf;
// set the swrst bit then zero all other bits in the register
UCA0CTL1 |= UCSWRST;
UCA0CTL1 &= UCSWRST;
UCA0CTL0 = 0x00;
UCA0CTL1 |= UCSSEL_2;
UCA0BR0 = 0x68;
UCA0BR1 = 0x00;
UCA0MCTL = 0x00;
UCA0MCTL |= (UCBRS_1 | UCBRF_0);
tbuf = UCA0RXBUF; // reset any pending interrupt conditions
tbuf = 0;
UCA0TXBUF = tbuf;
// now reset UART0's software reset bit to allow opperation
// this cannot be done until the above registers are initialized
UCA0CTL1 &= ~UCSWRST;
// enable UART0's receive interrupts
IE2 |= UCA0RXIE;
This section of code is the same for both board assemblies and there has been a wide variance of clocks ranging from 825KHz to 1.046 MHz. This causes the baud rate timing to be off and boards that fall too far below 1 MHz cannot communicate. The only way I can get the failing boards to communicate is to manually tweak UCA0BRx register values. I am seeing a variance of 86 - 109 in order to fix the boards that are not communicating. The firmware should be able use a fixed Baud Rate divider across all processors if the clock is stable. It is not acceptable to have custom firmware on every single board.
