We had a problem with the 5659 where the SFRIFG1_bit.OFIFG is never cleared.
After some work and having found no apparent reason the code below was tested in a 430F5659 and a 430F6659.
On the 6659 the flag is cleared while on the 5659 it's not.
Does anyone have any idea why this could be happening?? Any help is appreciated.
#include <io430.h>
static void SetVCoreUp( unsigned char level ) {
SVSMHCTL = SVSHE + SVSHRVL0 * level + SVMHE + SVSMHRRL0 * level;
SVSMLCTL = SVSLE + SVMLE + SVSMLRRL0 * level;
while ( ( PMMIFG & SVSMLDLYIFG ) == 0 ) {
}
PMMIFG &= ~( SVMLVLRIFG + SVMLIFG );
PMMCTL0_L = PMMCOREV0 * level;
if ( ( PMMIFG & SVMLIFG ) ) {
while ( ( PMMIFG & SVMLVLRIFG ) == 0 ) {
}
}
SVSMLCTL = SVSLE + SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level;
}
static void InitPMM( void ) {
PMMCTL0_H = PMMPW_H;
/* The SetVCoreUp procedure is implemented and used according to "2.2.4 Increasing Vcore to Support Higher MCLK Frequencies" */
if( (PMMCTL0 & (PMMCOREV1 | PMMCOREV0)) < PMMCOREV_1 ) {
SetVCoreUp( 1 );
}
if( (PMMCTL0 & (PMMCOREV1 | PMMCOREV0)) < PMMCOREV_2 ) {
SetVCoreUp( 2 );
}
if( (PMMCTL0 & (PMMCOREV1 | PMMCOREV0)) < PMMCOREV_3 ) {
SetVCoreUp( 3 );
}
SVSMLCTL = !SVMLE /* SVM high-side disabled */
| !SVSLE; /* SVS low-side disabled */
SVSMHCTL = !SVMHE /* SVM high-side disabled */
| !SVSHE; /* SVS high-side disabled */
PMMRIE = 0x00;
PMMCTL0_H = 0x00;
}
int main( void )
{
WDTCTL = (WDTPW | WDTHOLD); /* stop WDT */
InitPMM(); /* SVS, SVM, Vcore */
/* Clocks */
__bis_SR_register(SCG0); // Disable the FLL control loop
/* Clock module */
UCSCTL6 = XT2OFF // Turn off XT2
| XT1DRIVE_3 // Drive XT1 with the highest current for fast startup
| !XTS // XT1 in low frequency mode
| !XT1BYPASS // XT1 Sourced internally
| XCAP_3
| !SMCLKOFF // Turn on SMCLK
| !XT1OFF; // Turn on XT1
UCSCTL0 = 0x0900; // DCO tap = 9, MOD counter = 0
UCSCTL1 = DCORSEL_5 // For 6 to 23 MHz range
| !DISMOD; // Enable modulation
UCSCTL2 = FLLD__2 + 122; // Set DCO Multiplier for 8MHz
// D * (N + 1) * FLLRef = Fdco
// 2 * (122 + 1) * 32768 = 8MHz
UCSCTL3 = SELREF__XT1CLK // FLL reference set to XT1CLK (32768Hz)
| FLLREFDIV__1; // FLL reference divider /1
UCSCTL4 = SELA__XT1CLK // ACLK sourced by XT1CLK
| SELS__DCOCLK // SMCLK sourced by DCOCLK
| SELM__DCOCLK; // MCLK sourced by DCOCLK
UCSCTL5 = DIVPA__1 // ACLK divider to output pin /1
| DIVA__1 // ACLK divider /1
| DIVS__1 // SMCLK divider /1
| DIVM__1; // MCLK divider /1
UCSCTL8 = 0x0700 // Bits 8-10 require to be written in 1
| ACLKREQEN // Enable conditional module request signal for ACLK
| MCLKREQEN // Enable conditional module request signal for MCLK
| !SMCLKREQEN // Disable conditional module request signal for SMCLK
| !MODOSCREQEN; // Disable conditional module request
__bic_SR_register(SCG0); /* Enable the FLL control loop */
do {
UCSCTL7 &= ~(XT2OFFG | XT1LFOFFG | DCOFFG); /* Clear XT2, XT1, DCO fault flags */
SFRIFG1_bit.OFIFG = 0; /* Clear fault flags */
} while ( SFRIFG1_bit.OFIFG ); /* Test oscillator fault flag */
UCSCTL6 &= ~(XT1DRIVE0 | XT1DRIVE1); /* XT1 is now stable, reduce drive strength */
__bis_SR_register(SCG0); /* Disable the FLL control loop */
// Unreach code
for(;;);
}
