UART String Issue - String Data Missing

You are not configuring the clock system, so I guess SMCLK uses REFOCLK as reference, and runs at something that might be near 1 MHz.

Can you use the crystal instead?

Hi Clemens

I used the example code for the particular device, I did not change anything. I have done changes to the clock system to test it at 20MHz and I am getting the same problem, I am not using the crystal option as I need these pins for other functions, here is the updated code only changes are from 25MHz to 20MHz;

<code>
/*------------------------------------------------------------------------------
Standard Defined Libraries
------------------------------------------------------------------------------*/
#include <msp430.h>
#include <string.h>
#include <stdio.h>
/*------------------------------------------------------------------------------
Custom Defined Libraries
------------------------------------------------------------------------------*/
//
/*------------------------------------------------------------------------------
Function Prototypes
------------------------------------------------------------------------------*/
void DebugTxData (char *data); // Print Data to the Debug UART
void SetVcoreUp (unsigned int level); // SETUP -> CORE
/*------------------------------------------------------------------------------
Global Variables
------------------------------------------------------------------------------*/
char DebugReceivedData [256]; // DEBUG Responses Saved Here
int MilliSecondCounter; // Counter Reg For Milli-Second Delay
int SecondCounter; // Counter Reg for 1 Second Delay
/*------------------------------------------------------------------------------
Local Variables
------------------------------------------------------------------------------*/

/*------------------------------------------------------------------------------
MAIN ROUTINE
* Initialises MCU
------------------------------------------------------------------------------*/
int main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT to prevent WDT Reset for Start Up
//
PMAPPWD = 0x02D52; // Enable Write-access to modify port mapping registers
P4MAP7 = PM_MCLK;
PMAPPWD = 0; // Disable Write-Access to modify port mapping registers
// IO Set Up
P1DIR |= BIT1; // P1.1 output
P1DIR |= BIT0; // ACLK set out to pins
P1SEL |= BIT0;
// P2DIR |= BIT2; // SMCLK set out to pins
// P2SEL |= BIT2;
P4DIR |= BIT7; // MCLK set out to pins
P4SEL |= BIT7;
// SETUP DCO for 25MHz Operation
// Increase Vcore setting to level3 to support fsystem=25MHz
// NOTE: Change core voltage one level at a time..
SetVcoreUp (0x01);
SetVcoreUp (0x02);
SetVcoreUp (0x03);

UCSCTL3 = SELREF_2; // Set DCO FLL reference = REFO
UCSCTL4 |= SELA_2; // Set ACLK = REFO

__bis_SR_register(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_7; // Select DCO range 50MHz operation
UCSCTL2 |= FLLD_1 + 609; // Set DCO Multiplier for 20MHz
// (N + 1) * FLLRef = Fdco
// (609 + 1) * 32768 = 20MHz
// Set FLL Div = fDCOCLK/2
__bic_SR_register(SCG0); // Enable the FLL control loop

// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
// 32 x 32 x 20 MHz / 32,768 Hz ~ 625k MCLK cycles for DCO to settle
__delay_cycles(625000);

// Loop until XT1,XT2 & DCO stabilizes - In this case only DCO has to stabilize
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}
while (SFRIFG1&OFIFG); // Test oscillator fault flag
// UART Setup
P4DIR |= BIT4; // Set P4.4 as UART TX output
P4SEL |= BIT4+BIT5; // P4.4,5 = USCI_A0 TXD/RXD
UCA1CTL1 |= UCSWRST; // **Put state machine in reset**
UCA1CTL1 |= UCSSEL_2; // SMCLK
UCA1IRTCTL &= ~UCIREN; // Disable the IR Function
UCA1CTL0 &= ~UCPEN; // No Parity
UCA1CTL0 &= ~UCSPB; // 1 Stop BIT
UCA1CTL0 &= ~UC7BIT; // 8 BITS
UCA1CTL0 &= ~UCMSB; // LSB First
UCA1CTL0 &= ~UCSYNC; // Asynchronous Mode
UCA1CTL0 &= ~UCMODE0; // UART Mode
UCA1BR0 = 173; // 20MHz 115200 -> 173 (see User's Guide)
UCA1BR1 = 0; // 20MHz 115200
UCA1MCTL |= UCBRS_5 + UCBRF_0; // Modulation UCBRSx=5, UCBRFx=0
UCA1MCTL &= ~UCOS16; // Over sampling Not Selected
UCA1CTL1 &= ~UCSWRST; // **Initialise USCI state machine**
// UCA1IE |= UCRXIE; // Enable USCI_A0 RX interrupt
//
// __delay_cycles(6000000); // Delay
DebugReceivedData[0] = UCA1RXBUF; // Clear the Buffer
// OneSecDelay(); // Settle the system
__no_operation();
DebugTxData ("ABCDEFGHIJKLMNOPQRSTUVWXYZ123456789\r\n"); // DEBUG -> System Message
// Continuous LOOP
while(1)
{
P1OUT ^= BIT1; // Toggle P1.1
__delay_cycles(10000000); // 500 Milli-Second Delay
}
} // End Of Main Routine
/*------------------------------------------------------------------------------
END OF MAIN ROUTINE
------------------------------------------------------------------------------*/
//
/*------------------------------------------------------------------------------
DEBUG UART Send
* Checks Data length in routine
* RETURN: NONE
* PASS: STRING (CHAR)
* CALL: NONE
------------------------------------------------------------------------------*/
void DebugTxData (char *data)
{
// P1OUT ^= BIT6; // Toggle LED for debugging
unsigned int i;
unsigned int size = strlen(data); //get length of data to be sent
for (i = 0; i < size; i++)
{
while (!(UCTXIFG & UCA1IFG)); // Wait UART to finish before next send
while ((UCA1STAT & UCBUSY) != 0); // Test if TX BUFFER is NOT Busy
UCA1TXBUF = data[i]; // Send out on UART
}
// memset(data, '\0', i);
}
/*------------------------------------------------------------------------------
VCORE SETTINGS CHANGE
* RETURN: NONE
* PASS: "Level to be Set"
* CALL: NONE
------------------------------------------------------------------------------*/
void SetVcoreUp (unsigned int level)
{
// Open PMM registers for write
PMMCTL0_H = PMMPW_H;
// Set SVS/SVM high side new level
SVSMHCTL = SVSHE + SVSHRVL0 * level + SVMHE + SVSMHRRL0 * level;
// Set SVM low side to new level
SVSMLCTL = SVSLE + SVMLE + SVSMLRRL0 * level;
// Wait till SVM is settled
while ((PMMIFG & SVSMLDLYIFG) == 0);
// Clear already set flags
PMMIFG &= ~(SVMLVLRIFG + SVMLIFG);
// Set VCore to new level
PMMCTL0_L = PMMCOREV0 * level;
// Wait till new level reached
if ((PMMIFG & SVMLIFG))
while ((PMMIFG & SVMLVLRIFG) == 0);
// Set SVS/SVM low side to new level
SVSMLCTL = SVSLE + SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level;
// Lock PMM registers for write access
PMMCTL0_H = 0x00;
}

/*------------------------------------------------------------------------------
END OF PROGRAM
------------------------------------------------------------------------------*/

/*------------------------------------------------------------------------------
                Standard Defined Libraries
------------------------------------------------------------------------------*/
#include <msp430.h>
#include <string.h>
#include <stdio.h>
/*------------------------------------------------------------------------------
                Custom Defined Libraries
------------------------------------------------------------------------------*/
//
#define 	StartUp		"ABCDEFGHIJKLMNOPQRSTUVWXYZ\r\n"
/*------------------------------------------------------------------------------
                Function Prototypes
------------------------------------------------------------------------------*/
void DebugTxData (char *data);					// Print Data to the Debug UART
void SetVcoreUp (unsigned int level);			// SETUP -> CORE
/*------------------------------------------------------------------------------
                Global Variables
------------------------------------------------------------------------------*/
char DebugReceivedData [256];					// DEBUG Responses Saved Here
int  MilliSecondCounter;						// Counter Reg For Milli-Second Delay
int SecondCounter;								// Counter Reg for 1 Second Delay
/*------------------------------------------------------------------------------
                Local Variables
------------------------------------------------------------------------------*/

/*------------------------------------------------------------------------------
                        MAIN ROUTINE
 * Initialises MCU
------------------------------------------------------------------------------*/
int main(void)
{
	WDTCTL = WDTPW + WDTHOLD;               	// Stop WDT to prevent WDT Reset for Start Up
//
	PMAPPWD = 0x02D52;                        	// Enable Write-access to modify port mapping registers
	P4MAP7 = PM_MCLK;
	PMAPPWD = 0;                              	// Disable Write-Access to modify port mapping registers
// IO Set Up
	P1DIR |= BIT1;                            	// P1.1 output
	P1DIR |= BIT0;                            	// ACLK set out to pins
	P1SEL |= BIT0;
//	P2DIR |= BIT2;                            	// SMCLK set out to pins
//	P2SEL |= BIT2;
	P4DIR |= BIT7;                            	// MCLK set out to pins
	P4SEL |= BIT7;
// SETUP DCO for 25MHz Operation
	  // Increase Vcore setting to level3 to support fsystem=25MHz
	  // NOTE: Change core voltage one level at a time..
  SetVcoreUp (0x01);
  SetVcoreUp (0x02);
  SetVcoreUp (0x03);

  UCSCTL3 = SELREF_2;                       // Set DCO FLL reference = REFO
  UCSCTL4 |= SELA_2;                        // Set ACLK = REFO

  __bis_SR_register(SCG0);                  // Disable the FLL control loop
  UCSCTL0 = 0x0000;                         // Set lowest possible DCOx, MODx
  UCSCTL1 = DCORSEL_7;                      // Select DCO range 50MHz operation
  UCSCTL2 |= FLLD_1 + 609;                  // Set DCO Multiplier for 20MHz
                                            // (N + 1) * FLLRef = Fdco
                                            // (609 + 1) * 32768 = 20MHz
                                            // Set FLL Div = fDCOCLK/2
  __bic_SR_register(SCG0);                  // Enable the FLL control loop

 // Worst-case settling time for the DCO when the DCO range bits have been
 // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
 // UG for optimization.
  // 32 x 32 x 20 MHz / 32,768 Hz ~ 625k MCLK cycles for DCO to settle
  __delay_cycles(625000);

  // Loop until XT1,XT2 & DCO stabilizes - In this case only DCO has to stabilize
  do
  {
    UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);
                                            	// Clear XT2,XT1,DCO fault flags
    SFRIFG1 &= ~OFIFG;                      	// Clear fault flags
  }
  while (SFRIFG1&OFIFG);                   		// Test oscillator fault flag
//  UART Setup
	P4DIR |= BIT4;                            	// Set P4.4 as UART TX output
	P4SEL |= BIT4+BIT5;                       	// P4.4,5 = USCI_A0 TXD/RXD
	UCA1CTL1 |= UCSWRST;                      	// **Put state machine in reset**
	UCA1CTL1 |= UCSSEL_2;                     	// SMCLK
	UCA1IRTCTL &= ~UCIREN;						// Disable the IR Function
	UCA1CTL0 &= ~UCPEN;                     	// No Parity
	UCA1CTL0 &= ~UCSPB;                     	// 1 Stop BIT
	UCA1CTL0 &= ~UC7BIT;                     	// 8 BITS
	UCA1CTL0 &= ~UCMSB;                     	// LSB First
	UCA1CTL0 &= ~UCSYNC;                     	// Asynchronous Mode
	UCA1CTL0 &= ~UCMODE0;                     	// UART Mode
	UCA1BR0 = 173;                             	// 20MHz 115200 -> 173 (see User's Guide)
	UCA1BR1 = 0;                             	// 20MHz 115200
	UCA1MCTL |= UCBRS_5 + UCBRF_0;            	// Modulation UCBRSx=5, UCBRFx=0
	UCA1MCTL &= ~UCOS16;            			// Over sampling Not Selected
	UCA1CTL1 &= ~UCSWRST;                     	// **Initialise USCI state machine**
//	UCA1IE |= UCRXIE;                         	// Enable USCI_A0 RX interrupt
//
//    __delay_cycles(6000000);                 	// Delay
    DebugReceivedData[0] = UCA1RXBUF;			// Clear the Buffer
//	OneSecDelay();								// Settle the system
	__no_operation();
	DebugTxData (StartUp);						// DEBUG -> System Message
// Continuous LOOP
    while(1)
       {
        P1OUT ^= BIT1;                          // Toggle P1.1
        __delay_cycles(10000000);               // 500 Milli-Second Delay
       }
}												// End Of Main Routine
/*------------------------------------------------------------------------------
						END OF MAIN ROUTINE
------------------------------------------------------------------------------*/
//
/*------------------------------------------------------------------------------
                        DEBUG UART Send
  * Checks Data length in routine
  *	RETURN:				NONE
  *	PASS:				STRING (CHAR)
  *	CALL:				NONE
------------------------------------------------------------------------------*/
void DebugTxData (char *data)
 {
//     P1OUT ^= BIT6;  							// Toggle LED for debugging
     unsigned int i;
     unsigned int size = strlen(data);			//get length of data to be sent
     for (i = 0; i < size; i++)
     {
    	 while ((UCA1STAT & UCBUSY) != 0);		// Test if TX BUFFER is NOT Busy
    	 while (!(UCTXIFG & UCA1IFG));      	// Wait UART to finish before next send
         UCA1TXBUF = data[i];					// Send out on UART
     }
//     memset(data, '\0', size);
 }
/*------------------------------------------------------------------------------
                        VCORE SETTINGS CHANGE
  *	RETURN:				NONE
  *	PASS:				"Level to be Set"
  *	CALL:				NONE
------------------------------------------------------------------------------*/
void SetVcoreUp (unsigned int level)
{
  // Open PMM registers for write
  PMMCTL0_H = PMMPW_H;
  // Set SVS/SVM high side new level
  SVSMHCTL = SVSHE + SVSHRVL0 * level + SVMHE + SVSMHRRL0 * level;
  // Set SVM low side to new level
  SVSMLCTL = SVSLE + SVMLE + SVSMLRRL0 * level;
  // Wait till SVM is settled
  while ((PMMIFG & SVSMLDLYIFG) == 0);
  // Clear already set flags
  PMMIFG &= ~(SVMLVLRIFG + SVMLIFG);
  // Set VCore to new level
  PMMCTL0_L = PMMCOREV0 * level;
  // Wait till new level reached
  if ((PMMIFG & SVMLIFG))
    while ((PMMIFG & SVMLVLRIFG) == 0);
  // Set SVS/SVM low side to new level
  SVSMLCTL = SVSLE + SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level;
  // Lock PMM registers for write access
  PMMCTL0_H = 0x00;
}

/*------------------------------------------------------------------------------
						END OF PROGRAM
------------------------------------------------------------------------------*/

Hi Clemens

There is nothing here that is outside of the examples that are suggested on the Device page, I have updated the code to run at 20Mhz and the results are the same:

REFOCLK might not be very accurate. It does not matter what actual frequency you use for (S)MCLK, if the reference is off, the UART output will be off by the same percentage.

But I wonder why the first few bytes can be received correctly.
Could you insert a delay between the bytes to see what happens?

The longer a continuous communication the more off get your bytes. The first bytes can possibly be OK when the sampling time is still somewhere around the midpoint of the bit. But as more bytes you transmit, as more grows the difference until bits are sampled outside their position making a 0 to a 1, for example which can also cause the loss of the start-/stopp-bit.

Ok, added this in the While loop, and it only prints "A" and that is it, this delay is about 500mS between transmissions:

// Continuous LOOP
CharTest = 'A';
while(1)
{
while ((UCA1STAT & UCBUSY) != 0); // Test if TX BUFFER is NOT Busy
UCA1TXBUF = CharTest; // Send out on UART
P1OUT ^= BIT1; // Toggle P1.1
while (!(UCTXIFG & UCA1IFG)); // Wait UART to finish before next send
__delay_cycles(10000000); // 500 Milli-Second Delay
CharTest++;
if (CharTest >= '~')
{
CharTest = 'A';
}
}

Ok, tried all the above suggestions, have taken the Ti example and "copied and pasted", and that does not respond to an echoed character

/* --COPYRIGHT--,BSD_EX
* Copyright (c) 2013, Texas Instruments Incorporated
* All rights reserved.
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* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************
*
* MSP430 CODE EXAMPLE DISCLAIMER
*
* MSP430 code examples are self-contained low-level programs that typically
* demonstrate a single peripheral function or device feature in a highly
* concise manner. For this the code may rely on the device's power-on default
* register values and settings such as the clock configuration and care must
* be taken when combining code from several examples to avoid potential side
* effects. Also see www.ti.com/grace for a GUI- and www.ti.com/msp430ware
* for an API functional library-approach to peripheral configuration.
*
* --/COPYRIGHT--*/
//******************************************************************************
// MSP430F524x Demo - USCI_A0, 115200 UART Echo ISR, DCO SMCLK
//
// Description: Echo a received character, RX ISR used. Normal mode is LPM0.
// USCI_A0 RX interrupt triggers TX Echo.
// Baud rate divider with 1048576hz = 1048576/115200 = ~9.1 (009h|01h)
// ACLK = REFO = ~32768Hz, MCLK = SMCLK = default DCO = 32 x ACLK = 1048576Hz
// See User Guide for baud rate divider table
//
// MSP430F524x
// -----------------
// /|\| |
// | | |
// --|RST |
// | |
// | P3.3/UCA0TXD|------------>
// | | 115200 - 8N1
// | P3.4/UCA0RXD|<------------
//
// E. Chen
// Texas Instruments Inc.
// August 2013
// Built with IAR Embedded Workbench v5.52 & Code Composer Studio v5.5
//******************************************************************************

#include <msp430.h>

void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT

P3SEL |= BIT3+BIT4; // P3.3,4 = USCI_A0 TXD/RXD
UCA0CTL1 |= UCSWRST; // **Put state machine in reset**
UCA0CTL1 |= UCSSEL_2; // SMCLK
UCA0BR0 = 9; // 1MHz 115200 (see User's Guide)
UCA0BR1 = 0; // 1MHz 115200
UCA0MCTL |= UCBRS_1 + UCBRF_0; // Modulation UCBRSx=1, UCBRFx=0
UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
UCA0IE |= UCRXIE; // Enable USCI_A0 RX interrupt

__bis_SR_register(LPM0_bits + GIE); // Enter LPM0, interrupts enabled
__no_operation(); // For debugger
}

// Echo back RXed character, confirm TX buffer is ready first
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=USCI_A0_VECTOR
__interrupt void USCI_A0_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(USCI_A0_VECTOR))) USCI_A0_ISR (void)
#else
#error Compiler not supported!
#endif
{
switch(__even_in_range(UCA0IV,4))
{
case 0:break; // Vector 0 - no interrupt
case 2: // Vector 2 - RXIFG
while (!(UCA0IFG&UCTXIFG)); // USCI_A0 TX buffer ready?
UCA0TXBUF = UCA0RXBUF; // TX -> RXed character
break;
case 4:break; // Vector 4 - TXIFG
default: break;
}
}

Just a question, I have modified the lnk_msp430f5239.cmd file as below:

/*-----------------------------------------------------------------------------
-> Changes to RAM to configure Flag BITS for system management
using Structures
Original RAM Settings: RAM : origin = 0x2400, length = 0x2000
-------------------------------------------------------------------------------*/
GSM = 0x2400; // Cellular Management Flags -> 4 Bytes
MCU = 0x2404; // MCU Management Flags -> 4 Bytes
TRX = 0x2408; // RF Management Flags -> 4 Bytes
GPS = 0x240C; // GPS Management Flags -> 4 Bytes
EXP = 0x2410; // IO Expander Flags -> 4 Bytes
MSG = 0x2414; // Message Management Flags -> 4 Bytes
INP = 0x2418; // Input Control Flags -> 4 Bytes
RLY = 0x241C; // Output Control Flags -> 4 Bytes
DSY = 0x2420; // Display Management Flags -> 4 Bytes
SRV = 0x2424; // Server Management Flags -> 4 Bytes
UDS = 0x2428; // User Defined Flags -> 4 Bytes
MAN = 0x242C; // System Management Flags -> 4 Bytes
STU = 0x2430; // Send To User Flags -> 4 Bytes
EMG = 0x2434; // Email Management Flags -> 4 Bytes
NWO = 0x2438; // Network Management Flags -> 4 Bytes
/*-----------------------------------------------------------------------------*/
MEMORY
{
SFR : origin = 0x0000, length = 0x0010
PERIPHERALS_8BIT : origin = 0x0010, length = 0x00F0
PERIPHERALS_16BIT : origin = 0x0100, length = 0x0100
// RAM : origin = 0x2400, length = 0x2000 // Original Values
RAM : origin = 0x243C, length = 0x1FA0

Managed to get it working, deleted the project and started all over again. Built it up one piece at a time. Thanks for all the advice, the only difference to the above is that I am using 600 and not 609 in the FLL value, that seems to be an issue with corrupting data