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SPI buffer debugger

Hi All, 

I am trying to debug the following code. I am sending an array to the "UCB0TXBUF " . I setup a break point to see the values of UCB0TXBUF. But I am unable to see the values. The variable "i" increments fine. Any advise! jess

int main(void)
{
int i =0;
WDTCTL = WDTPW+WDTHOLD; // Stop watchdog timer


unsigned char command[] = {0xFF, 0xFE,0x05, 0x01,0x80,0xFE,0x01,0x00,0x7B};


P1OUT |= 0x02; // Set P1.0 for LED
// Set P1.1 for slave reset
P1DIR |= 0x03; // Set P1.0-2 to output direction
P3SEL |= 0xFF; // P3.5,4,0 option select

UCB0CTL1 |= UCSWRST; // **Put state machine in reset**
UCB0CTL0 |= UCMST+UCSYNC+UCCKPL+UCMSB; // 3-pin, 8-bit SPI master
// Clock polarity high, MSB
UCB0CTL1 |= UCSSEL_1; // SMCLK
UCB0BR0 = 0x02; // /2
UCB0BR1 = 0; //
// UCB0MCTL = 0; // No modulation
UCB0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
UCB0IE |= UCRXIE; // Enable USCI_A0 RX interrupt

P1OUT &= ~0x02; // Now with SPI signals initialized,
P1OUT |= 0x02; // reset slave

__delay_cycles(100); // Wait for slave to initialize

MST_Data = 0xAA; // Initialize data values
SLV_Data = 0xAA; //

while (!(UCB0IFG&UCTXIFG)); // USCI_A0 TX buffer ready?

while (i != 9)
{
UCB0TXBUF = command[i];
i++;
__delay_cycles(40);
}

__bis_SR_register(LPM0_bits + GIE); // CPU off, enable interrupts
}

  • which msp? and IAR or CCS?

    should it not be (you have 0xff):
    P3SEL |= 0x0C; // P3.3,2 option select

    http://coecsl.ece.illinois.edu/ge423/datasheets/MSP430Ref_Guides/Cexamples/MSP430G2xx3%20Code%20Examples/C/msp430g2xx3_uscib0_spi_09.c

    >UCB0IE |= UCRXIE; // Enable USCI_A0 RX interrupt
    Why, you are not using it,
    so the system could crash as vector is 0xffff and if GIE may be on.

    __delay_cycles(40);
    why not poll instead, the register is buffered and as soon IFG flag is set it can handle one more byte.

    Next step, learn how to never poll, but IRQ byte by byte.

  • TXBUF is a one-byte buffer, no FIFO or queue. Be sure that you only write to it, when its last content was properly handled. Instead of you 40 clock cycles delay, you should wait for TXIFG being set (indicating that the content is being processed and TXBUF can take another byte).
    If you fail to synchronize this process, you're just overwriting a memory cell multiple times.

    It makes no sens going into LPM0 after writing multiply bytes into TXBUF.
    You should rather enable the RX interrupt and go into LPM0, and each time TXBUF is ready for the next byte, the interrupt function (which you of course have to provide) is called and feeds the next byte into TXBUF, before returning to LPM0.

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