Oscillator fault interrupt and clock system lock - FR5969, cs_03 demo

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//******************************************************************************
//   MSP430FR59xx Demo - Output 32768Hz crystal on XT1 and observe failsafe
//
//   Description: Configure ACLK = LFXT1 and enter LPM3.
//   To observe failsafe behavior short the crystal briefly on the target board.
//   This will cause an NMI to occur. P1.0 is toggled inside the NMI ISR.
//   Once the fault flag is cleared XT1 operation continues from 32768Hz crystal
//   Otherwise ACLK defaults to LFMODCLK (~37.5KHz).
//   ACLK = LFXT1 = 32kHz, MCLK = SMCLK = 1MHz
//
//           MSP430FR59x
//         ---------------
//     /|\|            XIN|-
//      | |               | 32KHz Crystal
//      --|RST        XOUT|-
//        |               |
//        |           P2.0|---> ACLK = 32.768kHz (or 37.5kHz during LFXTOFFG)
//        |           P3.4|---> SMCLK = MCLK = 1MHz
//        |           P1.0|---> LED
//
//   P. Thanigai
//   Texas Instruments Inc.
//   August 2012
//   Built with Code Composer Studio V5.5
//******************************************************************************
#include <msp430.h>

volatile unsigned int temp0 = 0;
volatile unsigned int temp1 = 0;
volatile unsigned int temp2 = 0;

int main(void)
{
  WDTCTL = WDTPW | WDTHOLD;

  // GPIO Setup
  P1OUT = 0;
  P1DIR = BIT0;                             // For LED

  P2DIR |= BIT0;
  P2SEL0 |= BIT0;                           // Output ACLK
  P2SEL1 |= BIT0;

  P3DIR |= BIT4;
  P3SEL1 |= BIT4;                           // Output SMCLK

  PJSEL0 = BIT4 | BIT5;                     // For XT1

  // Disable the GPIO power-on default high-impedance mode to activate
  // previously configured port settings
  PM5CTL0 &= ~LOCKLPM5;

  // Clock System Setup
  CSCTL0_H = CSKEY >> 8;                    // Unlock CS registers
  CSCTL1 = DCOFSEL_0;                       // Set DCO to 1MHz
  CSCTL2 = SELA__LFXTCLK | SELS__DCOCLK | SELM__DCOCLK;
  CSCTL3 = DIVA__1 | DIVS__1 | DIVM__1;     // Set all dividers
  CSCTL4 &= ~LFXTOFF;
  do
  {
    CSCTL5 &= ~LFXTOFFG;                    // Clear XT1 fault flag
    SFRIFG1 &= ~OFIFG;
  }while (SFRIFG1&OFIFG);                   // Test oscillator fault flag

  CSCTL0_H = 0x00;	// Lock CS module (use byte mode to upper byte)

  // Now that osc is running enable fault interrupt
  SFRIE1 |= OFIE;

//  __bis_SR_register(LPM0_bits);             // Wait in LPM0 for fault flag
    __enable_interrupt();

  while (1) {
	    temp2 = CSCTL5 & LFXTOFFG;
  }
}

#pragma vector=UNMI_VECTOR
__interrupt void UNMI_ISR(void)
{
  do
  {
    // set a breakpoint on the line below to observe XT1 operating from VLO
    // when the breakpoint is hit during a crystal fault
	temp0 |= CSCTL5 & LFXTOFFG;
    CSCTL5 &= ~LFXTOFFG; // Break point 1
	temp1 |= CSCTL5 & LFXTOFFG;
    SFRIFG1 &= ~OFIFG; // Break point 2
    P1OUT |= BIT0;
    __delay_cycles(25000);                  // time for flag to get set again
  } while (SFRIFG1 & OFIFG);                   // Test oscillator fault flag

  P1OUT &= ~BIT0;
}