Hello everybody,
for my project i need a lot of memory pages and a lot of code. At the beginning i reserved 0x180 Byte (FRAM_RESERVED) at the end of my FRAM for later usage .
Now i need FRAM_RESERVED in the front of my code FRAM. But when i swap the 2 pieces i get the error "program will not fit into available memory. placement with alignment fails for section "ALL_FRAM" size 0x3a15".
My .map file says that the FRAM_RESERVED is completly unused and my FRAM has 0x1c unused memory. so why cant i swap that? I Have the feeling that ma FRAM needs more space then my .map says.
(I commented the new version out and let the working example inside.)
/* ============================================================================ */
/* Copyright (c) 2014, Texas Instruments Incorporated */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following conditions */
/* are met: */
/* */
/* * Redistributions of source code must retain the above copyright */
/* notice, this list of conditions and the following disclaimer. */
/* */
/* * Redistributions in binary form must reproduce the above copyright */
/* notice, this list of conditions and the following disclaimer in the */
/* documentation and/or other materials provided with the distribution. */
/* */
/* * Neither the name of Texas Instruments Incorporated nor the names of */
/* its contributors may be used to endorse or promote products derived */
/* from this software without specific prior written permission. */
/* */
/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */
/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */
/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */
/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */
/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */
/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */
/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */
/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */
/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */
/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ============================================================================ */
/******************************************************************************/
/* lnk_msp430fr5738.cmd - LINKER COMMAND FILE FOR LINKING MSP430FR5738 PROGRAMS */
/* */
/* Usage: lnk430 <obj files...> -o <out file> -m <map file> lnk.cmd */
/* cl430 <src files...> -z -o <out file> -m <map file> lnk.cmd */
/* */
/*----------------------------------------------------------------------------*/
/* These linker options are for command line linking only. For IDE linking, */
/* you should set your linker options in Project Properties */
/* -c LINK USING C CONVENTIONS */
/* -stack 0x0100 SOFTWARE STACK SIZE */
/* -heap 0x0100 HEAP AREA SIZE */
/* */
/*----------------------------------------------------------------------------*/
/* Version: 1.153 */
/*----------------------------------------------------------------------------*/
/****************************************************************************/
/* Specify the system memory map */
/****************************************************************************/
MEMORY
{
SFR : origin = 0x0000, length = 0x0010
PERIPHERALS_8BIT : origin = 0x0010, length = 0x00F0
PERIPHERALS_16BIT : origin = 0x0100, length = 0x0100
RAM : origin = 0x1C00, length = 0x0400
INFOA : origin = 0x1880, length = 0x0080
INFOB : origin = 0x1800, length = 0x0080
//2kB FRAM reserved from 0xC200
TXLOWMEM : origin = 0xC200, length = 0x0080
RXLOWMEM : origin = 0xC280, length = 0x0080
TXRXUPPMEM00 : origin = 0xC300, length = 0x0080
TXUPPMEM01 : origin = 0xC380, length = 0x0080
RXUPPMEM01 : origin = 0xC400, length = 0x0080
TXRXUPPMEM02 : origin = 0xC480, length = 0x0080
TXUPPMEM03 : origin = 0xC500, length = 0x0080
RXUPPMEM03 : origin = 0xC580, length = 0x0080
TXUPPMEM05 : origin = 0xC600, length = 0x0080
RXUPPMEM05 : origin = 0xC680, length = 0x0080
TXUPPMEM03_ROM : origin = 0xC700, length = 0x0080
RXUPPMEM03_ROM : origin = 0xC780, length = 0x0080
// FRAM_RESERVED : origin = 0xC800, length = 0x0180 //384B FRAM reserved to 0xC97F
// FRAM : origin = 0xC980, length = 0x3600 //
FRAM : origin = 0xC800, length = 0x3600
FRAM_RESERVED : origin = 0xFE00, length = 0x0180
JTAGSIGNATURE : origin = 0xFF80, length = 0x0004, fill = 0xFFFF
BSLSIGNATURE : origin = 0xFF84, length = 0x0004, fill = 0xFFFF
IPESIGNATURE : origin = 0xFF88, length = 0x0008, fill = 0xFFFF
INT00 : origin = 0xFF90, length = 0x0002
INT01 : origin = 0xFF92, length = 0x0002
INT02 : origin = 0xFF94, length = 0x0002
INT03 : origin = 0xFF96, length = 0x0002
INT04 : origin = 0xFF98, length = 0x0002
INT05 : origin = 0xFF9A, length = 0x0002
INT06 : origin = 0xFF9C, length = 0x0002
INT07 : origin = 0xFF9E, length = 0x0002
INT08 : origin = 0xFFA0, length = 0x0002
INT09 : origin = 0xFFA2, length = 0x0002
INT10 : origin = 0xFFA4, length = 0x0002
INT11 : origin = 0xFFA6, length = 0x0002
INT12 : origin = 0xFFA8, length = 0x0002
INT13 : origin = 0xFFAA, length = 0x0002
INT14 : origin = 0xFFAC, length = 0x0002
INT15 : origin = 0xFFAE, length = 0x0002
INT16 : origin = 0xFFB0, length = 0x0002
INT17 : origin = 0xFFB2, length = 0x0002
INT18 : origin = 0xFFB4, length = 0x0002
INT19 : origin = 0xFFB6, length = 0x0002
INT20 : origin = 0xFFB8, length = 0x0002
INT21 : origin = 0xFFBA, length = 0x0002
INT22 : origin = 0xFFBC, length = 0x0002
INT23 : origin = 0xFFBE, length = 0x0002
INT24 : origin = 0xFFC0, length = 0x0002
INT25 : origin = 0xFFC2, length = 0x0002
INT26 : origin = 0xFFC4, length = 0x0002
INT27 : origin = 0xFFC6, length = 0x0002
INT28 : origin = 0xFFC8, length = 0x0002
INT29 : origin = 0xFFCA, length = 0x0002
INT30 : origin = 0xFFCC, length = 0x0002
INT31 : origin = 0xFFCE, length = 0x0002
INT32 : origin = 0xFFD0, length = 0x0002
INT33 : origin = 0xFFD2, length = 0x0002
INT34 : origin = 0xFFD4, length = 0x0002
INT35 : origin = 0xFFD6, length = 0x0002
INT36 : origin = 0xFFD8, length = 0x0002
INT37 : origin = 0xFFDA, length = 0x0002
INT38 : origin = 0xFFDC, length = 0x0002
INT39 : origin = 0xFFDE, length = 0x0002
INT40 : origin = 0xFFE0, length = 0x0002
INT41 : origin = 0xFFE2, length = 0x0002
INT42 : origin = 0xFFE4, length = 0x0002
INT43 : origin = 0xFFE6, length = 0x0002
INT44 : origin = 0xFFE8, length = 0x0002
INT45 : origin = 0xFFEA, length = 0x0002
INT46 : origin = 0xFFEC, length = 0x0002
INT47 : origin = 0xFFEE, length = 0x0002
INT48 : origin = 0xFFF0, length = 0x0002
INT49 : origin = 0xFFF2, length = 0x0002
INT50 : origin = 0xFFF4, length = 0x0002
INT51 : origin = 0xFFF6, length = 0x0002
INT52 : origin = 0xFFF8, length = 0x0002
INT53 : origin = 0xFFFA, length = 0x0002
INT54 : origin = 0xFFFC, length = 0x0002
RESET : origin = 0xFFFE, length = 0x0002
}
/****************************************************************************/
/* Specify the sections allocation into memory */
/****************************************************************************/
SECTIONS
{
GROUP(ALL_FRAM)
{
GROUP(READ_WRITE_MEMORY)
{
.TI.persistent : {} /* For #pragma persistent */
.cio : {} /* C I/O buffer */
.sysmem : {} /* Dynamic memory allocation area */
} ALIGN(0x0200), RUN_START(fram_rw_start)
GROUP(READ_ONLY_MEMORY)
{
.cinit : {} /* Initialization tables */
.pinit : {} /* C++ constructor tables */
.init_array : {} /* C++ constructor tables */
.mspabi.exidx : {} /* C++ constructor tables */
.mspabi.extab : {} /* C++ constructor tables */
.const : {} /* Constant data */
} ALIGN(0x0200), RUN_START(fram_ro_start)
GROUP(EXECUTABLE_MEMORY)
{
.text : {} /* Code */
} ALIGN(0x0200), RUN_START(fram_rx_start)
} > FRAM
.jtagsignature : {} > JTAGSIGNATURE /* JTAG Signature */
.bslsignature : {} > BSLSIGNATURE /* BSL Signature */
.jtagpassword /* JTAG Password */
.bss : {} > RAM /* Global & static vars */
.data : {} > RAM /* Global & static vars */
.TI.noinit : {} > RAM /* For #pragma noinit */
.stack : {} > RAM (HIGH) /* Software system stack */
.infoA : {} > INFOA /* MSP430 INFO FRAM Memory segments */
.infoB : {} > INFOB
.txlowmem : {} > TXLOWMEM type = NOINIT
.rxlowmem : {} > RXLOWMEM type = NOINIT
.txrxuppmem00 : {} > TXRXUPPMEM00 type = NOINIT
.txuppmem01 : {} > TXUPPMEM01 type = NOINIT
.rxuppmem01 : {} > RXUPPMEM01 type = NOINIT
.txrxuppmem02 : {} > TXRXUPPMEM02 type = NOINIT
.txuppmem03 : {} > TXUPPMEM03 type = NOINIT
.rxuppmem03 : {} > RXUPPMEM03 type = NOINIT
.txuppmem05 : {} > TXUPPMEM05 type = NOINIT
.rxuppmem05 : {} > RXUPPMEM05 type = NOINIT
.txuppmem03_rom : {} > TXUPPMEM03_ROM type = NOINIT
.rxuppmem03_rom : {} > RXUPPMEM03_ROM type = NOINIT
//.txuppmem07 : {} > TXUPPMEM07 type = NOINIT
.fram_reserved : {} > FRAM_RESERVED type = NOINIT
/* MSP430 Interrupt vectors */
.int00 : {} > INT00
.int01 : {} > INT01
.int02 : {} > INT02
.int03 : {} > INT03
.int04 : {} > INT04
.int05 : {} > INT05
.int06 : {} > INT06
.int07 : {} > INT07
.int08 : {} > INT08
.int09 : {} > INT09
.int10 : {} > INT10
.int11 : {} > INT11
.int12 : {} > INT12
.int13 : {} > INT13
.int14 : {} > INT14
.int15 : {} > INT15
.int16 : {} > INT16
.int17 : {} > INT17
.int18 : {} > INT18
.int19 : {} > INT19
.int20 : {} > INT20
.int21 : {} > INT21
.int22 : {} > INT22
.int23 : {} > INT23
.int24 : {} > INT24
.int25 : {} > INT25
.int26 : {} > INT26
.int27 : {} > INT27
.int28 : {} > INT28
.int29 : {} > INT29
.int30 : {} > INT30
RTC : { * ( .int31 ) } > INT31 type = VECT_INIT
.int32 : {} > INT32
.int33 : {} > INT33
.int34 : {} > INT34
.int35 : {} > INT35
PORT2 : { * ( .int36 ) } > INT36 type = VECT_INIT
.int37 : {} > INT37
.int38 : {} > INT38
PORT1 : { * ( .int39 ) } > INT39 type = VECT_INIT
TIMER1_A1 : { * ( .int40 ) } > INT40 type = VECT_INIT
TIMER1_A0 : { * ( .int41 ) } > INT41 type = VECT_INIT
DMA : { * ( .int42 ) } > INT42 type = VECT_INIT
.int43 : {} > INT43
TIMER0_A1 : { * ( .int44 ) } > INT44 type = VECT_INIT
TIMER0_A0 : { * ( .int45 ) } > INT45 type = VECT_INIT
ADC10 : { * ( .int46 ) } > INT46 type = VECT_INIT
USCI_B0 : { * ( .int47 ) } > INT47 type = VECT_INIT
USCI_A0 : { * ( .int48 ) } > INT48 type = VECT_INIT
WDT : { * ( .int49 ) } > INT49 type = VECT_INIT
TIMER0_B1 : { * ( .int50 ) } > INT50 type = VECT_INIT
TIMER0_B0 : { * ( .int51 ) } > INT51 type = VECT_INIT
COMP_D : { * ( .int52 ) } > INT52 type = VECT_INIT
UNMI : { * ( .int53 ) } > INT53 type = VECT_INIT
SYSNMI : { * ( .int54 ) } > INT54 type = VECT_INIT
.reset : {} > RESET /* MSP430 Reset vector */
}
/****************************************************************************/
/* MPU Specific memory segment definitons */
/****************************************************************************/
#ifdef _MPU_ENABLE
#ifdef _MPU_MANUAL
mpusb1 = (_MPU_SEGB1 + 0x4000 - 0xFFFF - 1) * 32 / 0x4000 - 1;
mpusb2 = (_MPU_SEGB2 + 0x4000 - 0xFFFF - 1) * 32 / 0x4000 - 1;
__mpuseg = (mpusb2 << 8) | mpusb1;
__mpusam = (_MPU_SAM0 << 12) + (_MPU_SAM3 << 8) + (_MPU_SAM2 << 4) + _MPU_SAM1;
#else
mpusb1 = (fram_ro_start + 0x4000 - 0xFFFF - 1) * 32 / 0x4000 - 1;
mpusb2 = (fram_rx_start + 0x4000 - 0xFFFF - 1) * 32 / 0x4000 - 1;
__mpuseg = (mpusb2 << 8) | mpusb1;
__mpusam = 0x7513;
#endif
#endif
/****************************************************************************/
/* Include peripherals memory map */
/****************************************************************************/
-l msp430fr5738.cmd
******************************************************************************
MSP430 Linker PC v4.4.3
******************************************************************************
>> Linked Fri Feb 27 10:26:50 2015
OUTPUT FILE NAME: <PBeta_rev_3_0_0_10_msp430_OBT_live.out>
ENTRY POINT SYMBOL: "_c_int00_noargs_noexit" address: 0000fd0a
MEMORY CONFIGURATION
name origin length used unused attr fill
---------------------- -------- --------- -------- -------- ---- --------
SFR 00000000 00000010 00000000 00000010 RWIX
PERIPHERALS_8BIT 00000010 000000f0 00000000 000000f0 RWIX
PERIPHERALS_16BIT 00000100 00000100 00000000 00000100 RWIX
INFOB 00001800 00000080 00000000 00000080 RWIX
INFOA 00001880 00000080 00000000 00000080 RWIX
RAM 00001c00 00000400 0000014c 000002b4 RWIX
TXLOWMEM 0000c200 00000080 00000080 00000000 RWIX
RXLOWMEM 0000c280 00000080 00000080 00000000 RWIX
TXRXUPPMEM00 0000c300 00000080 00000080 00000000 RWIX
TXUPPMEM01 0000c380 00000080 00000080 00000000 RWIX
RXUPPMEM01 0000c400 00000080 00000080 00000000 RWIX
TXRXUPPMEM02 0000c480 00000080 00000080 00000000 RWIX
TXUPPMEM03 0000c500 00000080 00000080 00000000 RWIX
RXUPPMEM03 0000c580 00000080 00000080 00000000 RWIX
TXUPPMEM05 0000c600 00000080 00000080 00000000 RWIX
RXUPPMEM05 0000c680 00000080 00000080 00000000 RWIX
TXUPPMEM03_ROM 0000c700 00000080 00000080 00000000 RWIX
RXUPPMEM03_ROM 0000c780 00000080 00000080 00000000 RWIX
FRAM 0000c800 00003600 000035e4 0000001c RWIX
FRAM_RESERVED 0000fe00 00000180 00000000 00000180 RWIX
JTAGSIGNATURE 0000ff80 00000004 00000004 00000000 RWIX ffff
BSLSIGNATURE 0000ff84 00000004 00000004 00000000 RWIX ffff
IPESIGNATURE 0000ff88 00000008 00000008 00000000 RWIX ffff
INT00 0000ff90 00000002 00000000 00000002 RWIX
INT01 0000ff92 00000002 00000000 00000002 RWIX
INT02 0000ff94 00000002 00000000 00000002 RWIX
INT03 0000ff96 00000002 00000000 00000002 RWIX
INT04 0000ff98 00000002 00000000 00000002 RWIX
INT05 0000ff9a 00000002 00000000 00000002 RWIX
INT06 0000ff9c 00000002 00000000 00000002 RWIX
INT07 0000ff9e 00000002 00000000 00000002 RWIX
INT08 0000ffa0 00000002 00000000 00000002 RWIX
INT09 0000ffa2 00000002 00000000 00000002 RWIX
INT10 0000ffa4 00000002 00000000 00000002 RWIX
INT11 0000ffa6 00000002 00000000 00000002 RWIX
INT12 0000ffa8 00000002 00000000 00000002 RWIX
INT13 0000ffaa 00000002 00000000 00000002 RWIX
INT14 0000ffac 00000002 00000000 00000002 RWIX
INT15 0000ffae 00000002 00000000 00000002 RWIX
INT16 0000ffb0 00000002 00000000 00000002 RWIX
INT17 0000ffb2 00000002 00000000 00000002 RWIX
INT18 0000ffb4 00000002 00000000 00000002 RWIX
INT19 0000ffb6 00000002 00000000 00000002 RWIX
INT20 0000ffb8 00000002 00000000 00000002 RWIX
INT21 0000ffba 00000002 00000000 00000002 RWIX
INT22 0000ffbc 00000002 00000000 00000002 RWIX
INT23 0000ffbe 00000002 00000000 00000002 RWIX
INT24 0000ffc0 00000002 00000000 00000002 RWIX
INT25 0000ffc2 00000002 00000000 00000002 RWIX
INT26 0000ffc4 00000002 00000000 00000002 RWIX
INT27 0000ffc6 00000002 00000000 00000002 RWIX
INT28 0000ffc8 00000002 00000000 00000002 RWIX
INT29 0000ffca 00000002 00000000 00000002 RWIX
INT30 0000ffcc 00000002 00000000 00000002 RWIX
INT31 0000ffce 00000002 00000002 00000000 RWIX
INT32 0000ffd0 00000002 00000000 00000002 RWIX
INT33 0000ffd2 00000002 00000000 00000002 RWIX
INT34 0000ffd4 00000002 00000000 00000002 RWIX
INT35 0000ffd6 00000002 00000000 00000002 RWIX
INT36 0000ffd8 00000002 00000002 00000000 RWIX
INT37 0000ffda 00000002 00000000 00000002 RWIX
INT38 0000ffdc 00000002 00000000 00000002 RWIX
INT39 0000ffde 00000002 00000002 00000000 RWIX
INT40 0000ffe0 00000002 00000002 00000000 RWIX
INT41 0000ffe2 00000002 00000002 00000000 RWIX
INT42 0000ffe4 00000002 00000002 00000000 RWIX
INT43 0000ffe6 00000002 00000000 00000002 RWIX
INT44 0000ffe8 00000002 00000002 00000000 RWIX
INT45 0000ffea 00000002 00000002 00000000 RWIX
INT46 0000ffec 00000002 00000002 00000000 RWIX
INT47 0000ffee 00000002 00000002 00000000 RWIX
INT48 0000fff0 00000002 00000002 00000000 RWIX
INT49 0000fff2 00000002 00000002 00000000 RWIX
INT50 0000fff4 00000002 00000002 00000000 RWIX
INT51 0000fff6 00000002 00000002 00000000 RWIX
INT52 0000fff8 00000002 00000002 00000000 RWIX
INT53 0000fffa 00000002 00000002 00000000 RWIX
INT54 0000fffc 00000002 00000002 00000000 RWIX
RESET 0000fffe 00000002 00000002 00000000 RWIX
SECTION ALLOCATION MAP
output attributes/
section page origin length input sections
-------- ---- ---------- ---------- ----------------
.data 0 00001c00 00000065 UNINITIALIZED
00001c00 0000002c OBT_ADC.obj (.data)
00001c2c 00000020 OBT_Alarms.obj (.data)
00001c4c 00000016 OBT_I2C_Slave.obj (.data)
00001c62 00000002 OBT_Rx_modify.obj (.data)
00001c64 00000001 OBT_Main.obj (.data)
.bss 0 00001c66 00000047 UNINITIALIZED
00001c66 00000020 (.common:ADC_Result)
00001c86 00000020 (.common:DMA_Source)
00001ca6 00000006 (.common:gI2CWriteBuf)
00001cac 00000001 (.common:g_odd)
.stack 0 00001f60 000000a0 UNINITIALIZED
00001f60 00000002 rts430x_lc_sd_eabi.lib : boot.obj (.stack)
00001f62 0000009e --HOLE--
.txlowmem
* 0 0000c200 00000080
0000c200 00000080 OBT_codemem_init.obj (.txlowmem)
.rxlowmem
* 0 0000c280 00000080
0000c280 00000080 OBT_codemem_init.obj (.rxlowmem)
.txrxuppmem00
* 0 0000c300 00000080
0000c300 00000080 OBT_codemem_init.obj (.txrxuppmem00)
.txuppmem01
* 0 0000c380 00000080
0000c380 00000080 OBT_codemem_init.obj (.txuppmem01)
.rxuppmem01
* 0 0000c400 00000080
0000c400 00000080 OBT_codemem_init.obj (.rxuppmem01)
.txrxuppmem02
* 0 0000c480 00000080
0000c480 00000080 OBT_codemem_init.obj (.txrxuppmem02)
.txuppmem03
* 0 0000c500 00000080
0000c500 00000080 OBT_codemem_init.obj (.txuppmem03)
.rxuppmem03
* 0 0000c580 00000080
0000c580 00000080 OBT_codemem_init.obj (.rxuppmem03)
.txuppmem05
* 0 0000c600 00000080
0000c600 00000080 OBT_codemem_init.obj (.txuppmem05)
.rxuppmem05
* 0 0000c680 00000080
0000c680 00000080 OBT_codemem_init.obj (.rxuppmem05)
.txuppmem03_rom
* 0 0000c700 00000080
0000c700 00000080 OBT_codemem_init.obj (.txuppmem03_rom)
.rxuppmem03_rom
* 0 0000c780 00000080
0000c780 00000080 OBT_codemem_init.obj (.rxuppmem03_rom)
.TI.persistent
* 0 0000c800 00000000 UNINITIALIZED
.cio 0 0000c800 00000000 UNINITIALIZED
.sysmem 0 0000c800 00000000 UNINITIALIZED
.cinit 0 0000c800 00000034
0000c800 00000012 (.cinit..data.load) [load image, compression = rle]
0000c812 0000000c (__TI_handler_table)
0000c81e 00000006 (.cinit..bss.load) [load image, compression = zero_init]
0000c824 00000010 (__TI_cinit_table)
.pinit 0 0000c834 00000000 UNINITIALIZED
.init_array
* 0 0000c834 00000000 UNINITIALIZED
.mspabi.exidx
* 0 0000c834 00000000 UNINITIALIZED
.mspabi.extab
* 0 0000c834 00000000 UNINITIALIZED
.const 0 0000c834 00000000 UNINITIALIZED
.text 0 0000ca00 000033e4
0000ca00 00000c9a OBT_I2C_Slave.obj (.text:I2CWrite)
0000d69a 00000370 OBT_I2C_Slave.obj (.text:_isr:USCIB0_ISR)
0000da0a 00000368 OBT_Main.obj (.text:main)
0000dd72 000001a0 OBT_Alarms.obj (.text:CheckMonitors)
0000df12 0000013c OBT_Alarms.obj (.text:update_Intl)
0000e04e 00000130 OBT_Page_init.obj (.text:obt_copy_TxUppMem03_to_TxLowMem)
0000e17e 0000012c OBT_Tx_modify.obj (.text:MSP430_TxSetModeSel)
0000e2aa 0000011a OBT_I2C_Slave.obj (.text:UpdatePswdMatchFlags)
0000e3c4 00000116 OBT_Main.obj (.text:TRX_INIT_STATE)
0000e4da 00000106 OBT_Page_init.obj (.text:obt_copy_RxUppMem03_to_RxLowMem)
0000e5e0 000000f8 OBT_Alarms.obj (.text:CheckRxIRQ)
0000e6d8 000000f8 OBT_Rx_modify.obj (.text:MSP430_RxCoarseEval)
0000e7d0 000000f4 OBT_Rx_modify.obj (.text:MSP430_Rx_init)
0000e8c4 000000e0 OBT_Tx_modify.obj (.text:MSP430_Tx_init)
0000e9a4 000000de OBT_ADC.obj (.text:MSP430_DMA_init)
0000ea82 000000d6 rts430x_lc_sd_eabi.lib : copy_decompress_rle.obj (.text:__TI_decompress_rle_core$10)
0000eb58 000000c6 OBT_Tx_modify.obj (.text:MSP430_TxCDREna)
0000ec1e 000000c4 OBT_Tx_modify.obj (.text:MSP430_TxSingleInputOffsetCali)
0000ece2 000000b8 OBT_Tx_modify.obj (.text:MSP430_Tx_setEqLvl)
0000ed9a 000000aa OBT_Rx_modify.obj (.text:MSP430_RxChConfDis)
0000ee44 000000a6 OBT_Rx_modify.obj (.text:MSP430_RxPolFlip)
0000eeea 000000a2 OBT_I2C_Master.obj (.text:MSP430_I2CMST_getRxAddresses)
0000ef8c 000000a2 OBT_I2C_Master.obj (.text:MSP430_I2CMST_getTxAddresses)
0000f02e 000000a2 OBT_Rx_modify.obj (.text:MSP430_RxCDREna)
0000f0d0 0000009c OBT_Rx_modify.obj (.text:MSP430_Rx_setOutLvl)
0000f16c 00000092 OBT_I2C_Master.obj (.text:MSP430_I2CMST_readMoreFromSlave)
0000f1fe 00000092 OBT_Tx_modify.obj (.text:MSP430_TxChConfDis)
0000f290 00000090 OBT_Tx_modify.obj (.text:MSP430_TxSetDefault)
0000f320 0000008e OBT_Tx_modify.obj (.text:MSP430_TxCDR_Init)
0000f3ae 00000086 OBT_Tx_modify.obj (.text:MSP430_TxPolFlip)
0000f434 00000084 OBT_Rx_modify.obj (.text:MSP430_RxCDR_Init)
0000f4b8 00000080 rts430x_lc_sd_eabi.lib : autoinit_wdt.obj (.text:_auto_init_hold_wdt)
0000f538 0000007e OBT_I2C_Master.obj (.text:MSP430_I2CMST_readFromSlave)
0000f5b6 0000007c OBT_ADC.obj (.text:MSP430_ADC_VHI)
0000f632 0000007c OBT_ADC.obj (.text:MSP430_ADC_VRX)
0000f6ae 0000007a OBT_Page_init.obj (.text:obt_init_Rx_LowMem)
0000f728 0000007a OBT_Page_init.obj (.text:obt_init_Tx_LowMem)
0000f7a2 00000078 OBT_I2C_Master.obj (.text:MSP430_I2CMST_writeByte)
0000f81a 00000070 OBT_ADC.obj (.text:MSP430_ADC_VCC)
0000f88a 00000070 OBT_I2C_Master.obj (.text:MSP430_I2CMST_writeMoreOnSlave)
0000f8fa 00000070 OBT_I2C_Slave.obj (.text:init_i2c_slave)
0000f96a 0000006c OBT_I2C_Master.obj (.text:MSP430_I2CMST_readByte)
0000f9d6 00000066 OBT_I2C_Master.obj (.text:MSP430_I2CMST_writeOnSlave)
0000fa3c 00000056 OBT_I2C_Master.obj (.text:MSP430_I2CMST_findSlaves)
0000fa92 00000054 OBT_ADC.obj (.text:MSP430_ADC_Temp)
0000fae6 00000040 rts430x_lc_sd_eabi.lib : cpy_util.obj (.text:__memcpy_far)
0000fb26 0000003e : copy_zero_init.obj (.text:decompress:ZI:__TI_zero_init)
0000fb64 0000003e : asr32.obj (.text:l_asr_const)
0000fba2 0000003e : lsl32.obj (.text:l_lsl_const)
0000fbe0 0000003e : lsr32.obj (.text:l_lsr_const)
0000fc1e 0000003c : copy_decompress_none.obj (.text:decompress:none:__TI_decompress_none)
0000fc5a 00000034 OBT_I2C_Master.obj (.text:INT_I2C_Analyze_NACK)
0000fc8e 0000002e OBT_Main.obj (.text:_isr:ADC10_ISR)
0000fcbc 0000002c rts430x_lc_sd_eabi.lib : div16s.obj (.text)
0000fce8 00000022 : mult32_f5hw.obj (.text)
0000fd0a 0000001a : boot_special.obj (.text:_isr:_c_int00_noargs_noexit)
0000fd24 0000001a OBT_Page_init.obj (.text:obt_init_Tx_UppMem05)
0000fd3e 00000018 OBT_Page_init.obj (.text:obt_init_Rx_UppMem03)
0000fd56 00000018 OBT_Page_init.obj (.text:obt_init_Tx_UppMem03)
0000fd6e 00000016 rts430x_lc_sd_eabi.lib : div16u.obj (.text)
0000fd84 00000016 : mult16_f5hw.obj (.text)
0000fd9a 00000010 OBT_I2C_Slave.obj (.text:write_to_fram)
0000fdaa 0000000e rts430x_lc_sd_eabi.lib : copy_decompress_rle.obj (.text:decompress:rle24:__TI_decompress_rle24)
0000fdb8 0000000a : asr16.obj (.text)
0000fdc2 0000000a : lsl16.obj (.text)
0000fdcc 0000000a : lsr16.obj (.text)
0000fdd6 00000006 : isr_trap.obj (.text:_isr:__TI_ISR_TRAP)
0000fddc 00000004 : pre_init.obj (.text:_system_pre_init)
0000fde0 00000004 : exit.obj (.text:abort)
RTC 0 0000ffce 00000002
0000ffce 00000002 rts430x_lc_sd_eabi.lib : int31.obj (.int31)
PORT2 0 0000ffd8 00000002
0000ffd8 00000002 rts430x_lc_sd_eabi.lib : int36.obj (.int36)
$fill000 0 0000ff80 00000004
0000ff80 00000004 --HOLE-- [fill = ffff]
$fill001 0 0000ff84 00000004
0000ff84 00000004 --HOLE-- [fill = ffff]
$fill002 0 0000ff88 00000008
0000ff88 00000008 --HOLE-- [fill = ffff]
PORT1 0 0000ffde 00000002
0000ffde 00000002 rts430x_lc_sd_eabi.lib : int39.obj (.int39)
TIMER1_A1
* 0 0000ffe0 00000002
0000ffe0 00000002 rts430x_lc_sd_eabi.lib : int40.obj (.int40)
TIMER1_A0
* 0 0000ffe2 00000002
0000ffe2 00000002 rts430x_lc_sd_eabi.lib : int41.obj (.int41)
DMA 0 0000ffe4 00000002
0000ffe4 00000002 rts430x_lc_sd_eabi.lib : int42.obj (.int42)
TIMER0_A1
* 0 0000ffe8 00000002
0000ffe8 00000002 rts430x_lc_sd_eabi.lib : int44.obj (.int44)
TIMER0_A0
* 0 0000ffea 00000002
0000ffea 00000002 rts430x_lc_sd_eabi.lib : int45.obj (.int45)
ADC10 0 0000ffec 00000002
0000ffec 00000002 <whole-program> (.int46)
USCI_B0 0 0000ffee 00000002
0000ffee 00000002 <whole-program> (.int47)
USCI_A0 0 0000fff0 00000002
0000fff0 00000002 rts430x_lc_sd_eabi.lib : int48.obj (.int48)
WDT 0 0000fff2 00000002
0000fff2 00000002 rts430x_lc_sd_eabi.lib : int49.obj (.int49)
TIMER0_B1
* 0 0000fff4 00000002
0000fff4 00000002 rts430x_lc_sd_eabi.lib : int50.obj (.int50)
TIMER0_B0
* 0 0000fff6 00000002
0000fff6 00000002 rts430x_lc_sd_eabi.lib : int51.obj (.int51)
COMP_D 0 0000fff8 00000002
0000fff8 00000002 rts430x_lc_sd_eabi.lib : int52.obj (.int52)
UNMI 0 0000fffa 00000002
0000fffa 00000002 rts430x_lc_sd_eabi.lib : int53.obj (.int53)
SYSNMI 0 0000fffc 00000002
0000fffc 00000002 rts430x_lc_sd_eabi.lib : int54.obj (.int54)
.reset 0 0000fffe 00000002
0000fffe 00000002 rts430x_lc_sd_eabi.lib : boot.obj (.reset)
LINKER GENERATED COPY TABLES
__TI_cinit_table @ 0000c824 records: 2, size/record: 8, table size: 16
.data: load addr=0000c800, load size=00000012 bytes, run addr=00001c00, run size=00000065 bytes, compression=rle
.bss: load addr=0000c81e, load size=00000006 bytes, run addr=00001c66, run size=00000047 bytes, compression=zero_init
LINKER GENERATED HANDLER TABLE
__TI_handler_table @ 0000c812 records: 3, size/record: 4, table size: 12
index: 0, handler: __TI_zero_init
index: 1, handler: __TI_decompress_rle24
index: 2, handler: __TI_decompress_none
GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name
address name
------- ----
00000700 ADC10CTL0
00000701 ADC10CTL0_H
00000700 ADC10CTL0_L
00000702 ADC10CTL1
00000703 ADC10CTL1_H
00000702 ADC10CTL1_L
00000704 ADC10CTL2
00000705 ADC10CTL2_H
00000704 ADC10CTL2_L
00000708 ADC10HI
00000709 ADC10HI_H
00000708 ADC10HI_L
0000071a ADC10IE
0000071b ADC10IE_H
0000071a ADC10IE_L
0000071c ADC10IFG
0000071d ADC10IFG_H
0000071c ADC10IFG_L
0000071e ADC10IV
0000071f ADC10IV_H
0000071e ADC10IV_L
00000706 ADC10LO
00000707 ADC10LO_H
00000706 ADC10LO_L
0000070a ADC10MCTL0
0000070b ADC10MCTL0_H
0000070a ADC10MCTL0_L
00000712 ADC10MEM0
00000713 ADC10MEM0_H
00000712 ADC10MEM0_L
0000fc8e ADC10_ISR
00001c66 ADC_Result
00001c04 ADC_Temp_Offset
00001c02 ADC_Temp_Slope
00001c08 ADC_VCC_Offset
000004be BCD2BIN
000004bc BIN2BCD
00001c53 BlockIntI2C
0000fde0 C$$EXIT
000008c0 CDCTL0
000008c1 CDCTL0_H
000008c0 CDCTL0_L
000008c2 CDCTL1
000008c3 CDCTL1_H
000008c2 CDCTL1_L
000008c4 CDCTL2
000008c5 CDCTL2_H
000008c4 CDCTL2_L
000008c6 CDCTL3
000008c7 CDCTL3_H
000008c6 CDCTL3_L
000008cc CDINT
000008cd CDINT_H
000008cc CDINT_L
000008ce CDIV
000008cf CDIV_H
000008ce CDIV_L
00000150 CRCDI
00000152 CRCDIRB
00000153 CRCDIRB_H
00000152 CRCDIRB_L
00000151 CRCDI_H
00000150 CRCDI_L
00000154 CRCINIRES
00000155 CRCINIRES_H
00000154 CRCINIRES_L
00000156 CRCRESR
00000157 CRCRESR_H
00000156 CRCRESR_L
00000160 CSCTL0
00000161 CSCTL0_H
00000160 CSCTL0_L
00000162 CSCTL1
00000163 CSCTL1_H
00000162 CSCTL1_L
00000164 CSCTL2
00000165 CSCTL2_H
00000164 CSCTL2_L
00000166 CSCTL3
00000167 CSCTL3_H
00000166 CSCTL3_L
00000168 CSCTL4
00000169 CSCTL4_H
00000168 CSCTL4_L
0000016a CSCTL5
0000016b CSCTL5_H
0000016a CSCTL5_L
0000016c CSCTL6
0000016d CSCTL6_H
0000016c CSCTL6_L
0000dd72 CheckMonitors
0000e5e0 CheckRxIRQ
00000510 DMA0CTL
00000511 DMA0CTL_H
00000510 DMA0CTL_L
00000516 DMA0DA
00000518 DMA0DAH
00000516 DMA0DAL
00000512 DMA0SA
00000514 DMA0SAH
00000512 DMA0SAL
0000051a DMA0SZ
00000520 DMA1CTL
00000521 DMA1CTL_H
00000520 DMA1CTL_L
00000526 DMA1DA
00000528 DMA1DAH
00000526 DMA1DAL
00000522 DMA1SA
00000524 DMA1SAH
00000522 DMA1SAL
0000052a DMA1SZ
00000530 DMA2CTL
00000531 DMA2CTL_H
00000530 DMA2CTL_L
00000536 DMA2DA
00000538 DMA2DAH
00000536 DMA2DAL
00000532 DMA2SA
00000534 DMA2SAH
00000532 DMA2SAL
0000053a DMA2SZ
00000500 DMACTL0
00000501 DMACTL0_H
00000500 DMACTL0_L
00000502 DMACTL1
00000503 DMACTL1_H
00000502 DMACTL1_L
00000504 DMACTL2
00000505 DMACTL2_H
00000504 DMACTL2_L
00000506 DMACTL3
00000507 DMACTL3_H
00000506 DMACTL3_L
00000508 DMACTL4
00000509 DMACTL4_H
00000508 DMACTL4_L
0000050e DMAIV
0000050f DMAIV_H
0000050e DMAIV_L
00001c86 DMA_Source
00000140 FRCTL0
00000141 FRCTL0_H
00000140 FRCTL0_L
00000144 GCCTL0
00000145 GCCTL0_H
00000144 GCCTL0_L
00000146 GCCTL1
00000147 GCCTL1_H
00000146 GCCTL1_L
0000ca00 I2CWrite
0000fc5a INT_I2C_Analyze_NACK
000004c4 MAC
000004da MAC32H
000004db MAC32H_H
000004da MAC32H_L
000004d8 MAC32L
000004d9 MAC32L_H
000004d8 MAC32L_L
000004c6 MACS
000004de MACS32H
000004df MACS32H_H
000004de MACS32H_L
000004dc MACS32L
000004dd MACS32L_H
000004dc MACS32L_L
000004c7 MACS_H
000004c6 MACS_L
000004c5 MAC_H
000004c4 MAC_L
000005a0 MPUCTL0
000005a1 MPUCTL0_H
000005a0 MPUCTL0_L
000005a2 MPUCTL1
000005a3 MPUCTL1_H
000005a2 MPUCTL1_L
000005a6 MPUSAM
000005a7 MPUSAM_H
000005a6 MPUSAM_L
000005a4 MPUSEG
000005a5 MPUSEG_H
000005a4 MPUSEG_L
000004c0 MPY
000004ec MPY32CTL0
000004ed MPY32CTL0_H
000004ec MPY32CTL0_L
000004d2 MPY32H
000004d3 MPY32H_H
000004d2 MPY32H_L
000004d0 MPY32L
000004d1 MPY32L_H
000004d0 MPY32L_L
000004c2 MPYS
000004d6 MPYS32H
000004d7 MPYS32H_H
000004d6 MPYS32H_L
000004d4 MPYS32L
000004d5 MPYS32L_H
000004d4 MPYS32L_L
000004c3 MPYS_H
000004c2 MPYS_L
000004c1 MPY_H
000004c0 MPY_L
0000fa92 MSP430_ADC_Temp
0000f81a MSP430_ADC_VCC
0000f5b6 MSP430_ADC_VHI
0000f632 MSP430_ADC_VRX
0000e9a4 MSP430_DMA_init
0000fa3c MSP430_I2CMST_findSlaves
0000eeea MSP430_I2CMST_getRxAddresses
0000ef8c MSP430_I2CMST_getTxAddresses
0000f96a MSP430_I2CMST_readByte
0000f538 MSP430_I2CMST_readFromSlave
0000f16c MSP430_I2CMST_readMoreFromSlave
0000f7a2 MSP430_I2CMST_writeByte
0000f88a MSP430_I2CMST_writeMoreOnSlave
0000f9d6 MSP430_I2CMST_writeOnSlave
0000f02e MSP430_RxCDREna
0000f434 MSP430_RxCDR_Init
0000ed9a MSP430_RxChConfDis
0000e6d8 MSP430_RxCoarseEval
0000ee44 MSP430_RxPolFlip
0000e7d0 MSP430_Rx_init
0000f0d0 MSP430_Rx_setOutLvl
0000eb58 MSP430_TxCDREna
0000f320 MSP430_TxCDR_Init
0000f1fe MSP430_TxChConfDis
0000f3ae MSP430_TxPolFlip
0000f290 MSP430_TxSetDefault
0000e17e MSP430_TxSetModeSel
0000ec1e MSP430_TxSingleInputOffsetCali
0000e8c4 MSP430_Tx_init
0000ece2 MSP430_Tx_setEqLvl
000004c8 OP2
000004e2 OP2H
000004e3 OP2H_H
000004e2 OP2H_L
000004e0 OP2L
000004e1 OP2L_H
000004e0 OP2L_L
000004c9 OP2_H
000004c8 OP2_L
0000020e P1IV
0000021e P2IV
00000204 PADIR
00000205 PADIR_H
00000204 PADIR_L
0000021a PAIE
00000218 PAIES
00000219 PAIES_H
00000218 PAIES_L
0000021b PAIE_H
0000021a PAIE_L
0000021c PAIFG
0000021d PAIFG_H
0000021c PAIFG_L
00000200 PAIN
00000201 PAIN_H
00000200 PAIN_L
00000202 PAOUT
00000203 PAOUT_H
00000202 PAOUT_L
00000206 PAREN
00000207 PAREN_H
00000206 PAREN_L
0000020a PASEL0
0000020b PASEL0_H
0000020a PASEL0_L
0000020c PASEL1
0000020d PASEL1_H
0000020c PASEL1_L
00000216 PASELC
00000217 PASELC_H
00000216 PASELC_L
00000324 PJDIR
00000325 PJDIR_H
00000324 PJDIR_L
00000320 PJIN
00000321 PJIN_H
00000320 PJIN_L
00000322 PJOUT
00000323 PJOUT_H
00000322 PJOUT_L
00000326 PJREN
00000327 PJREN_H
00000326 PJREN_L
0000032a PJSEL0
0000032b PJSEL0_H
0000032a PJSEL0_L
0000032c PJSEL1
0000032d PJSEL1_H
0000032c PJSEL1_L
00000336 PJSELC
00000337 PJSELC_H
00000336 PJSELC_L
00000130 PM5CTL0
00000131 PM5CTL0_H
00000130 PM5CTL0_L
00000120 PMMCTL0
00000121 PMMCTL0_H
00000120 PMMCTL0_L
0000012a PMMIFG
0000012b PMMIFG_H
0000012a PMMIFG_L
000001b0 REFCTL0
000001b1 REFCTL0_H
000001b0 REFCTL0_L
000004e4 RES0
000004e5 RES0_H
000004e4 RES0_L
000004e6 RES1
000004e7 RES1_H
000004e6 RES1_L
000004e8 RES2
000004e9 RES2_H
000004e8 RES2_L
000004ea RES3
000004eb RES3_H
000004ea RES3_L
000004cc RESHI
000004cd RESHI_H
000004cc RESHI_L
000004ca RESLO
000004cb RESLO_H
000004ca RESLO_L
000004ba RTCADOWDAY
000004bb RTCADOWDAY_H
000004ba RTCADOWDAY_L
000004b8 RTCAMINHR
000004b9 RTCAMINHR_H
000004b8 RTCAMINHR_L
000004a0 RTCCTL01
000004a1 RTCCTL01_H
000004a0 RTCCTL01_L
000004a2 RTCCTL23
000004a3 RTCCTL23_H
000004a2 RTCCTL23_L
000004b4 RTCDATE
000004b5 RTCDATE_H
000004b4 RTCDATE_L
000004ae RTCIV
000004ac RTCPS
000004a8 RTCPS0CTL
000004a9 RTCPS0CTL_H
000004a8 RTCPS0CTL_L
000004aa RTCPS1CTL
000004ab RTCPS1CTL_H
000004aa RTCPS1CTL_L
000004ad RTCPS_H
000004ac RTCPS_L
000004b0 RTCTIM0
000004b1 RTCTIM0_H
000004b0 RTCTIM0_L
000004b2 RTCTIM1
000004b3 RTCTIM1_H
000004b2 RTCTIM1_L
000004b6 RTCYEAR
000004b7 RTCYEAR_H
000004b6 RTCYEAR_L
00001c5e RX_ADDR
00001c56 RX_CDR_Quick_Mod
0000c280 Rx_LowMem
00001c62 Rx_Thr_Coarse_status
0000c400 Rx_UppMem01
0000c580 Rx_UppMem03
0000c780 Rx_UppMem03_ROM
0000c680 Rx_UppMem05
00000100 SFRIE1
00000101 SFRIE1_H
00000100 SFRIE1_L
00000102 SFRIFG1
00000103 SFRIFG1_H
00000102 SFRIFG1_L
00000104 SFRRPCR
00000105 SFRRPCR_H
00000104 SFRRPCR_L
00001c64 STATE
000004ce SUMEXT
000004cf SUMEXT_H
000004ce SUMEXT_L
00000198 SYSBERRIV
00000199 SYSBERRIV_H
00000198 SYSBERRIV_L
00000182 SYSBSLC
00000183 SYSBSLC_H
00000182 SYSBSLC_L
00000180 SYSCTL
00000181 SYSCTL_H
00000180 SYSCTL_L
00000186 SYSJMBC
00000187 SYSJMBC_H
00000186 SYSJMBC_L
00000188 SYSJMBI0
00000189 SYSJMBI0_H
00000188 SYSJMBI0_L
0000018a SYSJMBI1
0000018b SYSJMBI1_H
0000018a SYSJMBI1_L
0000018c SYSJMBO0
0000018d SYSJMBO0_H
0000018c SYSJMBO0_L
0000018e SYSJMBO1
0000018f SYSJMBO1_H
0000018e SYSJMBO1_L
0000019e SYSRSTIV
0000019f SYSRSTIV_H
0000019e SYSRSTIV_L
0000019c SYSSNIV
0000019d SYSSNIV_H
0000019c SYSSNIV_L
0000019a SYSUNIV
0000019b SYSUNIV_H
0000019a SYSUNIV_L
00000352 TA0CCR0
00000354 TA0CCR1
00000356 TA0CCR2
00000342 TA0CCTL0
00000344 TA0CCTL1
00000346 TA0CCTL2
00000340 TA0CTL
00000360 TA0EX0
0000036e TA0IV
00000350 TA0R
00000392 TA1CCR0
00000394 TA1CCR1
00000396 TA1CCR2
00000382 TA1CCTL0
00000384 TA1CCTL1
00000386 TA1CCTL2
00000380 TA1CTL
000003a0 TA1EX0
000003ae TA1IV
00000390 TA1R
000003d2 TB0CCR0
000003d4 TB0CCR1
000003d6 TB0CCR2
000003c2 TB0CCTL0
000003c4 TB0CCTL1
000003c6 TB0CCTL2
000003c0 TB0CTL
000003e0 TB0EX0
000003ee TB0IV
000003d0 TB0R
0000e3c4 TRX_INIT_STATE
00001c5d TX_ADDR
00001c54 TX_CDR_Quick_Mod
0000c300 TxRx_UppMem00
0000c480 TxRx_UppMem02
0000c200 Tx_LowMem
0000c380 Tx_UppMem01
0000c500 Tx_UppMem03
0000c700 Tx_UppMem03_ROM
0000c600 Tx_UppMem05
000005d0 UCA0ABCTL
000005c6 UCA0BRW
000005c7 UCA0BRW_H
000005c6 UCA0BRW_L
000005c0 UCA0CTLW0
000005c1 UCA0CTLW0_H
000005c0 UCA0CTLW0_L
000005c2 UCA0CTLW1
000005c3 UCA0CTLW1_H
000005c2 UCA0CTLW1_L
000005da UCA0IE
000005db UCA0IE_H
000005da UCA0IE_L
000005dc UCA0IFG
000005dd UCA0IFG_H
000005dc UCA0IFG_L
000005d2 UCA0IRCTL
000005d3 UCA0IRCTL_H
000005d2 UCA0IRCTL_L
000005de UCA0IV
000005c8 UCA0MCTLW
000005c9 UCA0MCTLW_H
000005c8 UCA0MCTLW_L
000005cc UCA0RXBUF
000005cd UCA0RXBUF_H
000005cc UCA0RXBUF_L
000005ca UCA0STATW
000005ce UCA0TXBUF
000005cf UCA0TXBUF_H
000005ce UCA0TXBUF_L
0000065e UCB0ADDMASK
0000065f UCB0ADDMASK_H
0000065e UCB0ADDMASK_L
0000065c UCB0ADDRX
00001c60 UCB0ADDRX_BACKUP
0000065d UCB0ADDRX_H
0000065c UCB0ADDRX_L
00000646 UCB0BRW
00000647 UCB0BRW_H
00000646 UCB0BRW_L
00000640 UCB0CTLW0
00000641 UCB0CTLW0_H
00000640 UCB0CTLW0_L
00000642 UCB0CTLW1
00000643 UCB0CTLW1_H
00000642 UCB0CTLW1_L
00000654 UCB0I2COA0
00000655 UCB0I2COA0_H
00000654 UCB0I2COA0_L
00000656 UCB0I2COA1
00000657 UCB0I2COA1_H
00000656 UCB0I2COA1_L
00000658 UCB0I2COA2
00000659 UCB0I2COA2_H
00000658 UCB0I2COA2_L
0000065a UCB0I2COA3
0000065b UCB0I2COA3_H
0000065a UCB0I2COA3_L
00000660 UCB0I2CSA
00000661 UCB0I2CSA_H
00000660 UCB0I2CSA_L
0000066a UCB0IE
0000066b UCB0IE_H
0000066a UCB0IE_L
0000066c UCB0IFG
0000066d UCB0IFG_H
0000066c UCB0IFG_L
0000066e UCB0IV
0000064c UCB0RXBUF
0000064d UCB0RXBUF_H
0000064c UCB0RXBUF_L
00000648 UCB0STATW
00000649 UCB0STATW_H
00000648 UCB0STATW_L
0000064a UCB0TBCNT
0000064b UCB0TBCNT_H
0000064a UCB0TBCNT_L
0000064e UCB0TXBUF
0000064f UCB0TXBUF_H
0000064e UCB0TXBUF_L
0000d69a USCIB0_ISR
00001c3b UnLatched_RxFlags
00001c2c UnLatched_TxFlags
00001c4a Unlatched_RxAVGLIM
0000e2aa UpdatePswdMatchFlags
0000015c WDTCTL
0000015d WDTCTL_H
0000015c WDTCTL_L
00002000 __STACK_END
000000a0 __STACK_SIZE
0000c824 __TI_CINIT_Base
0000c834 __TI_CINIT_Limit
0000c812 __TI_Handler_Table_Base
0000c81e __TI_Handler_Table_Limit
UNDEFED __TI_INITARRAY_Base
UNDEFED __TI_INITARRAY_Limit
0000fdd6 __TI_ISR_TRAP
0000fc1e __TI_decompress_none
0000fdaa __TI_decompress_rle24
0000ffce __TI_int31
0000ffd8 __TI_int36
0000ffde __TI_int39
0000ffe0 __TI_int40
0000ffe2 __TI_int41
0000ffe4 __TI_int42
0000ffe8 __TI_int44
0000ffea __TI_int45
0000ffec __TI_int46
0000ffee __TI_int47
0000fff0 __TI_int48
0000fff2 __TI_int49
0000fff4 __TI_int50
0000fff6 __TI_int51
0000fff8 __TI_int52
0000fffa __TI_int53
0000fffc __TI_int54
0000fb26 __TI_zero_init
ffffffff __binit__
ffffffff __c_args__
0000fae6 __memcpy_far
0000fcbc __mspabi_divi
0000fd6e __mspabi_divu
0000fd84 __mspabi_mpyi_f5hw
0000fce8 __mspabi_mpyl_f5hw
0000fcbc __mspabi_remi
0000fd6e __mspabi_remu
0000fdc2 __mspabi_slli
0000fbda __mspabi_slll_1
0000fbb6 __mspabi_slll_10
0000fbb2 __mspabi_slll_11
0000fbae __mspabi_slll_12
0000fbaa __mspabi_slll_13
0000fba6 __mspabi_slll_14
0000fba2 __mspabi_slll_15
0000fbd6 __mspabi_slll_2
0000fbd2 __mspabi_slll_3
0000fbce __mspabi_slll_4
0000fbca __mspabi_slll_5
0000fbc6 __mspabi_slll_6
0000fbc2 __mspabi_slll_7
0000fbbe __mspabi_slll_8
0000fbba __mspabi_slll_9
0000fdb8 __mspabi_srai
0000fb9c __mspabi_sral_1
0000fb78 __mspabi_sral_10
0000fb74 __mspabi_sral_11
0000fb70 __mspabi_sral_12
0000fb6c __mspabi_sral_13
0000fb68 __mspabi_sral_14
0000fb64 __mspabi_sral_15
0000fb98 __mspabi_sral_2
0000fb94 __mspabi_sral_3
0000fb90 __mspabi_sral_4
0000fb8c __mspabi_sral_5
0000fb88 __mspabi_sral_6
0000fb84 __mspabi_sral_7
0000fb80 __mspabi_sral_8
0000fb7c __mspabi_sral_9
0000fdcc __mspabi_srli
0000fc18 __mspabi_srll_1
0000fbf4 __mspabi_srll_10
0000fbf0 __mspabi_srll_11
0000fbec __mspabi_srll_12
0000fbe8 __mspabi_srll_13
0000fbe4 __mspabi_srll_14
0000fbe0 __mspabi_srll_15
0000fc14 __mspabi_srll_2
0000fc10 __mspabi_srll_3
0000fc0c __mspabi_srll_4
0000fc08 __mspabi_srll_5
0000fc04 __mspabi_srll_6
0000fc00 __mspabi_srll_7
0000fbfc __mspabi_srll_8
0000fbf8 __mspabi_srll_9
0000f4b8 _auto_init_hold_wdt
0000fd0a _c_int00_noargs_noexit
0000fffe _reset_vector
00001f60 _stack
0000fddc _system_pre_init
0000fde0 abort
ffffffff binit
0000c800 fram_ro_start
0000c800 fram_rw_start
0000ca00 fram_rx_start
00001c50 gHostPasswdChk
00001ca6 gI2CWriteBuf
00001c4e gI2CWriteCnt
00001c4c gI2CWriteRdy
00001c52 gModLPagePWChk
00001c51 gModPasswdChk
00001cac g_odd
0000f8fa init_i2c_slave
0000da0a main
0000e4da obt_copy_RxUppMem03_to_RxLowMem
0000e04e obt_copy_TxUppMem03_to_TxLowMem
0000f6ae obt_init_Rx_LowMem
0000fd3e obt_init_Rx_UppMem03
0000f728 obt_init_Tx_LowMem
0000fd56 obt_init_Tx_UppMem03
0000fd24 obt_init_Tx_UppMem05
00001c58 sI2CMemAdrBuf_A0
00001c5a sI2CMemAdrBuf_A8
00001c5c sI2C_Start_Detected
00001c00 temp
0000df12 update_Intl
0000fd9a write_to_fram
GLOBAL SYMBOLS: SORTED BY Symbol Address
address name
------- ----
000000a0 __STACK_SIZE
00000100 SFRIE1
00000100 SFRIE1_L
00000101 SFRIE1_H
00000102 SFRIFG1
00000102 SFRIFG1_L
00000103 SFRIFG1_H
00000104 SFRRPCR
00000104 SFRRPCR_L
00000105 SFRRPCR_H
00000120 PMMCTL0
00000120 PMMCTL0_L
00000121 PMMCTL0_H
0000012a PMMIFG
0000012a PMMIFG_L
0000012b PMMIFG_H
00000130 PM5CTL0
00000130 PM5CTL0_L
00000131 PM5CTL0_H
00000140 FRCTL0
00000140 FRCTL0_L
00000141 FRCTL0_H
00000144 GCCTL0
00000144 GCCTL0_L
00000145 GCCTL0_H
00000146 GCCTL1
00000146 GCCTL1_L
00000147 GCCTL1_H
00000150 CRCDI
00000150 CRCDI_L
00000151 CRCDI_H
00000152 CRCDIRB
00000152 CRCDIRB_L
00000153 CRCDIRB_H
00000154 CRCINIRES
00000154 CRCINIRES_L
00000155 CRCINIRES_H
00000156 CRCRESR
00000156 CRCRESR_L
00000157 CRCRESR_H
0000015c WDTCTL
0000015c WDTCTL_L
0000015d WDTCTL_H
00000160 CSCTL0
00000160 CSCTL0_L
00000161 CSCTL0_H
00000162 CSCTL1
00000162 CSCTL1_L
00000163 CSCTL1_H
00000164 CSCTL2
00000164 CSCTL2_L
00000165 CSCTL2_H
00000166 CSCTL3
00000166 CSCTL3_L
00000167 CSCTL3_H
00000168 CSCTL4
00000168 CSCTL4_L
00000169 CSCTL4_H
0000016a CSCTL5
0000016a CSCTL5_L
0000016b CSCTL5_H
0000016c CSCTL6
0000016c CSCTL6_L
0000016d CSCTL6_H
00000180 SYSCTL
00000180 SYSCTL_L
00000181 SYSCTL_H
00000182 SYSBSLC
00000182 SYSBSLC_L
00000183 SYSBSLC_H
00000186 SYSJMBC
00000186 SYSJMBC_L
00000187 SYSJMBC_H
00000188 SYSJMBI0
00000188 SYSJMBI0_L
00000189 SYSJMBI0_H
0000018a SYSJMBI1
0000018a SYSJMBI1_L
0000018b SYSJMBI1_H
0000018c SYSJMBO0
0000018c SYSJMBO0_L
0000018d SYSJMBO0_H
0000018e SYSJMBO1
0000018e SYSJMBO1_L
0000018f SYSJMBO1_H
00000198 SYSBERRIV
00000198 SYSBERRIV_L
00000199 SYSBERRIV_H
0000019a SYSUNIV
0000019a SYSUNIV_L
0000019b SYSUNIV_H
0000019c SYSSNIV
0000019c SYSSNIV_L
0000019d SYSSNIV_H
0000019e SYSRSTIV
0000019e SYSRSTIV_L
0000019f SYSRSTIV_H
000001b0 REFCTL0
000001b0 REFCTL0_L
000001b1 REFCTL0_H
00000200 PAIN
00000200 PAIN_L
00000201 PAIN_H
00000202 PAOUT
00000202 PAOUT_L
00000203 PAOUT_H
00000204 PADIR
00000204 PADIR_L
00000205 PADIR_H
00000206 PAREN
00000206 PAREN_L
00000207 PAREN_H
0000020a PASEL0
0000020a PASEL0_L
0000020b PASEL0_H
0000020c PASEL1
0000020c PASEL1_L
0000020d PASEL1_H
0000020e P1IV
00000216 PASELC
00000216 PASELC_L
00000217 PASELC_H
00000218 PAIES
00000218 PAIES_L
00000219 PAIES_H
0000021a PAIE
0000021a PAIE_L
0000021b PAIE_H
0000021c PAIFG
0000021c PAIFG_L
0000021d PAIFG_H
0000021e P2IV
00000320 PJIN
00000320 PJIN_L
00000321 PJIN_H
00000322 PJOUT
00000322 PJOUT_L
00000323 PJOUT_H
00000324 PJDIR
00000324 PJDIR_L
00000325 PJDIR_H
00000326 PJREN
00000326 PJREN_L
00000327 PJREN_H
0000032a PJSEL0
0000032a PJSEL0_L
0000032b PJSEL0_H
0000032c PJSEL1
0000032c PJSEL1_L
0000032d PJSEL1_H
00000336 PJSELC
00000336 PJSELC_L
00000337 PJSELC_H
00000340 TA0CTL
00000342 TA0CCTL0
00000344 TA0CCTL1
00000346 TA0CCTL2
00000350 TA0R
00000352 TA0CCR0
00000354 TA0CCR1
00000356 TA0CCR2
00000360 TA0EX0
0000036e TA0IV
00000380 TA1CTL
00000382 TA1CCTL0
00000384 TA1CCTL1
00000386 TA1CCTL2
00000390 TA1R
00000392 TA1CCR0
00000394 TA1CCR1
00000396 TA1CCR2
000003a0 TA1EX0
000003ae TA1IV
000003c0 TB0CTL
000003c2 TB0CCTL0
000003c4 TB0CCTL1
000003c6 TB0CCTL2
000003d0 TB0R
000003d2 TB0CCR0
000003d4 TB0CCR1
000003d6 TB0CCR2
000003e0 TB0EX0
000003ee TB0IV
000004a0 RTCCTL01
000004a0 RTCCTL01_L
000004a1 RTCCTL01_H
000004a2 RTCCTL23
000004a2 RTCCTL23_L
000004a3 RTCCTL23_H
000004a8 RTCPS0CTL
000004a8 RTCPS0CTL_L
000004a9 RTCPS0CTL_H
000004aa RTCPS1CTL
000004aa RTCPS1CTL_L
000004ab RTCPS1CTL_H
000004ac RTCPS
000004ac RTCPS_L
000004ad RTCPS_H
000004ae RTCIV
000004b0 RTCTIM0
000004b0 RTCTIM0_L
000004b1 RTCTIM0_H
000004b2 RTCTIM1
000004b2 RTCTIM1_L
000004b3 RTCTIM1_H
000004b4 RTCDATE
000004b4 RTCDATE_L
000004b5 RTCDATE_H
000004b6 RTCYEAR
000004b6 RTCYEAR_L
000004b7 RTCYEAR_H
000004b8 RTCAMINHR
000004b8 RTCAMINHR_L
000004b9 RTCAMINHR_H
000004ba RTCADOWDAY
000004ba RTCADOWDAY_L
000004bb RTCADOWDAY_H
000004bc BIN2BCD
000004be BCD2BIN
000004c0 MPY
000004c0 MPY_L
000004c1 MPY_H
000004c2 MPYS
000004c2 MPYS_L
000004c3 MPYS_H
000004c4 MAC
000004c4 MAC_L
000004c5 MAC_H
000004c6 MACS
000004c6 MACS_L
000004c7 MACS_H
000004c8 OP2
000004c8 OP2_L
000004c9 OP2_H
000004ca RESLO
000004ca RESLO_L
000004cb RESLO_H
000004cc RESHI
000004cc RESHI_L
000004cd RESHI_H
000004ce SUMEXT
000004ce SUMEXT_L
000004cf SUMEXT_H
000004d0 MPY32L
000004d0 MPY32L_L
000004d1 MPY32L_H
000004d2 MPY32H
000004d2 MPY32H_L
000004d3 MPY32H_H
000004d4 MPYS32L
000004d4 MPYS32L_L
000004d5 MPYS32L_H
000004d6 MPYS32H
000004d6 MPYS32H_L
000004d7 MPYS32H_H
000004d8 MAC32L
000004d8 MAC32L_L
000004d9 MAC32L_H
000004da MAC32H
000004da MAC32H_L
000004db MAC32H_H
000004dc MACS32L
000004dc MACS32L_L
000004dd MACS32L_H
000004de MACS32H
000004de MACS32H_L
000004df MACS32H_H
000004e0 OP2L
000004e0 OP2L_L
000004e1 OP2L_H
000004e2 OP2H
000004e2 OP2H_L
000004e3 OP2H_H
000004e4 RES0
000004e4 RES0_L
000004e5 RES0_H
000004e6 RES1
000004e6 RES1_L
000004e7 RES1_H
000004e8 RES2
000004e8 RES2_L
000004e9 RES2_H
000004ea RES3
000004ea RES3_L
000004eb RES3_H
000004ec MPY32CTL0
000004ec MPY32CTL0_L
000004ed MPY32CTL0_H
00000500 DMACTL0
00000500 DMACTL0_L
00000501 DMACTL0_H
00000502 DMACTL1
00000502 DMACTL1_L
00000503 DMACTL1_H
00000504 DMACTL2
00000504 DMACTL2_L
00000505 DMACTL2_H
00000506 DMACTL3
00000506 DMACTL3_L
00000507 DMACTL3_H
00000508 DMACTL4
00000508 DMACTL4_L
00000509 DMACTL4_H
0000050e DMAIV
0000050e DMAIV_L
0000050f DMAIV_H
00000510 DMA0CTL
00000510 DMA0CTL_L
00000511 DMA0CTL_H
00000512 DMA0SA
00000512 DMA0SAL
00000514 DMA0SAH
00000516 DMA0DA
00000516 DMA0DAL
00000518 DMA0DAH
0000051a DMA0SZ
00000520 DMA1CTL
00000520 DMA1CTL_L
00000521 DMA1CTL_H
00000522 DMA1SA
00000522 DMA1SAL
00000524 DMA1SAH
00000526 DMA1DA
00000526 DMA1DAL
00000528 DMA1DAH
0000052a DMA1SZ
00000530 DMA2CTL
00000530 DMA2CTL_L
00000531 DMA2CTL_H
00000532 DMA2SA
00000532 DMA2SAL
00000534 DMA2SAH
00000536 DMA2DA
00000536 DMA2DAL
00000538 DMA2DAH
0000053a DMA2SZ
000005a0 MPUCTL0
000005a0 MPUCTL0_L
000005a1 MPUCTL0_H
000005a2 MPUCTL1
000005a2 MPUCTL1_L
000005a3 MPUCTL1_H
000005a4 MPUSEG
000005a4 MPUSEG_L
000005a5 MPUSEG_H
000005a6 MPUSAM
000005a6 MPUSAM_L
000005a7 MPUSAM_H
000005c0 UCA0CTLW0
000005c0 UCA0CTLW0_L
000005c1 UCA0CTLW0_H
000005c2 UCA0CTLW1
000005c2 UCA0CTLW1_L
000005c3 UCA0CTLW1_H
000005c6 UCA0BRW
000005c6 UCA0BRW_L
000005c7 UCA0BRW_H
000005c8 UCA0MCTLW
000005c8 UCA0MCTLW_L
000005c9 UCA0MCTLW_H
000005ca UCA0STATW
000005cc UCA0RXBUF
000005cc UCA0RXBUF_L
000005cd UCA0RXBUF_H
000005ce UCA0TXBUF
000005ce UCA0TXBUF_L
000005cf UCA0TXBUF_H
000005d0 UCA0ABCTL
000005d2 UCA0IRCTL
000005d2 UCA0IRCTL_L
000005d3 UCA0IRCTL_H
000005da UCA0IE
000005da UCA0IE_L
000005db UCA0IE_H
000005dc UCA0IFG
000005dc UCA0IFG_L
000005dd UCA0IFG_H
000005de UCA0IV
00000640 UCB0CTLW0
00000640 UCB0CTLW0_L
00000641 UCB0CTLW0_H
00000642 UCB0CTLW1
00000642 UCB0CTLW1_L
00000643 UCB0CTLW1_H
00000646 UCB0BRW
00000646 UCB0BRW_L
00000647 UCB0BRW_H
00000648 UCB0STATW
00000648 UCB0STATW_L
00000649 UCB0STATW_H
0000064a UCB0TBCNT
0000064a UCB0TBCNT_L
0000064b UCB0TBCNT_H
0000064c UCB0RXBUF
0000064c UCB0RXBUF_L
0000064d UCB0RXBUF_H
0000064e UCB0TXBUF
0000064e UCB0TXBUF_L
0000064f UCB0TXBUF_H
00000654 UCB0I2COA0
00000654 UCB0I2COA0_L
00000655 UCB0I2COA0_H
00000656 UCB0I2COA1
00000656 UCB0I2COA1_L
00000657 UCB0I2COA1_H
00000658 UCB0I2COA2
00000658 UCB0I2COA2_L
00000659 UCB0I2COA2_H
0000065a UCB0I2COA3
0000065a UCB0I2COA3_L
0000065b UCB0I2COA3_H
0000065c UCB0ADDRX
0000065c UCB0ADDRX_L
0000065d UCB0ADDRX_H
0000065e UCB0ADDMASK
0000065e UCB0ADDMASK_L
0000065f UCB0ADDMASK_H
00000660 UCB0I2CSA
00000660 UCB0I2CSA_L
00000661 UCB0I2CSA_H
0000066a UCB0IE
0000066a UCB0IE_L
0000066b UCB0IE_H
0000066c UCB0IFG
0000066c UCB0IFG_L
0000066d UCB0IFG_H
0000066e UCB0IV
00000700 ADC10CTL0
00000700 ADC10CTL0_L
00000701 ADC10CTL0_H
00000702 ADC10CTL1
00000702 ADC10CTL1_L
00000703 ADC10CTL1_H
00000704 ADC10CTL2
00000704 ADC10CTL2_L
00000705 ADC10CTL2_H
00000706 ADC10LO
00000706 ADC10LO_L
00000707 ADC10LO_H
00000708 ADC10HI
00000708 ADC10HI_L
00000709 ADC10HI_H
0000070a ADC10MCTL0
0000070a ADC10MCTL0_L
0000070b ADC10MCTL0_H
00000712 ADC10MEM0
00000712 ADC10MEM0_L
00000713 ADC10MEM0_H
0000071a ADC10IE
0000071a ADC10IE_L
0000071b ADC10IE_H
0000071c ADC10IFG
0000071c ADC10IFG_L
0000071d ADC10IFG_H
0000071e ADC10IV
0000071e ADC10IV_L
0000071f ADC10IV_H
000008c0 CDCTL0
000008c0 CDCTL0_L
000008c1 CDCTL0_H
000008c2 CDCTL1
000008c2 CDCTL1_L
000008c3 CDCTL1_H
000008c4 CDCTL2
000008c4 CDCTL2_L
000008c5 CDCTL2_H
000008c6 CDCTL3
000008c6 CDCTL3_L
000008c7 CDCTL3_H
000008cc CDINT
000008cc CDINT_L
000008cd CDINT_H
000008ce CDIV
000008ce CDIV_L
000008cf CDIV_H
00001c00 temp
00001c02 ADC_Temp_Slope
00001c04 ADC_Temp_Offset
00001c08 ADC_VCC_Offset
00001c2c UnLatched_TxFlags
00001c3b UnLatched_RxFlags
00001c4a Unlatched_RxAVGLIM
00001c4c gI2CWriteRdy
00001c4e gI2CWriteCnt
00001c50 gHostPasswdChk
00001c51 gModPasswdChk
00001c52 gModLPagePWChk
00001c53 BlockIntI2C
00001c54 TX_CDR_Quick_Mod
00001c56 RX_CDR_Quick_Mod
00001c58 sI2CMemAdrBuf_A0
00001c5a sI2CMemAdrBuf_A8
00001c5c sI2C_Start_Detected
00001c5d TX_ADDR
00001c5e RX_ADDR
00001c60 UCB0ADDRX_BACKUP
00001c62 Rx_Thr_Coarse_status
00001c64 STATE
00001c66 ADC_Result
00001c86 DMA_Source
00001ca6 gI2CWriteBuf
00001cac g_odd
00001f60 _stack
00002000 __STACK_END
0000c200 Tx_LowMem
0000c280 Rx_LowMem
0000c300 TxRx_UppMem00
0000c380 Tx_UppMem01
0000c400 Rx_UppMem01
0000c480 TxRx_UppMem02
0000c500 Tx_UppMem03
0000c580 Rx_UppMem03
0000c600 Tx_UppMem05
0000c680 Rx_UppMem05
0000c700 Tx_UppMem03_ROM
0000c780 Rx_UppMem03_ROM
0000c800 fram_ro_start
0000c800 fram_rw_start
0000c812 __TI_Handler_Table_Base
0000c81e __TI_Handler_Table_Limit
0000c824 __TI_CINIT_Base
0000c834 __TI_CINIT_Limit
0000ca00 I2CWrite
0000ca00 fram_rx_start
0000d69a USCIB0_ISR
0000da0a main
0000dd72 CheckMonitors
0000df12 update_Intl
0000e04e obt_copy_TxUppMem03_to_TxLowMem
0000e17e MSP430_TxSetModeSel
0000e2aa UpdatePswdMatchFlags
0000e3c4 TRX_INIT_STATE
0000e4da obt_copy_RxUppMem03_to_RxLowMem
0000e5e0 CheckRxIRQ
0000e6d8 MSP430_RxCoarseEval
0000e7d0 MSP430_Rx_init
0000e8c4 MSP430_Tx_init
0000e9a4 MSP430_DMA_init
0000eb58 MSP430_TxCDREna
0000ec1e MSP430_TxSingleInputOffsetCali
0000ece2 MSP430_Tx_setEqLvl
0000ed9a MSP430_RxChConfDis
0000ee44 MSP430_RxPolFlip
0000eeea MSP430_I2CMST_getRxAddresses
0000ef8c MSP430_I2CMST_getTxAddresses
0000f02e MSP430_RxCDREna
0000f0d0 MSP430_Rx_setOutLvl
0000f16c MSP430_I2CMST_readMoreFromSlave
0000f1fe MSP430_TxChConfDis
0000f290 MSP430_TxSetDefault
0000f320 MSP430_TxCDR_Init
0000f3ae MSP430_TxPolFlip
0000f434 MSP430_RxCDR_Init
0000f4b8 _auto_init_hold_wdt
0000f538 MSP430_I2CMST_readFromSlave
0000f5b6 MSP430_ADC_VHI
0000f632 MSP430_ADC_VRX
0000f6ae obt_init_Rx_LowMem
0000f728 obt_init_Tx_LowMem
0000f7a2 MSP430_I2CMST_writeByte
0000f81a MSP430_ADC_VCC
0000f88a MSP430_I2CMST_writeMoreOnSlave
0000f8fa init_i2c_slave
0000f96a MSP430_I2CMST_readByte
0000f9d6 MSP430_I2CMST_writeOnSlave
0000fa3c MSP430_I2CMST_findSlaves
0000fa92 MSP430_ADC_Temp
0000fae6 __memcpy_far
0000fb26 __TI_zero_init
0000fb64 __mspabi_sral_15
0000fb68 __mspabi_sral_14
0000fb6c __mspabi_sral_13
0000fb70 __mspabi_sral_12
0000fb74 __mspabi_sral_11
0000fb78 __mspabi_sral_10
0000fb7c __mspabi_sral_9
0000fb80 __mspabi_sral_8
0000fb84 __mspabi_sral_7
0000fb88 __mspabi_sral_6
0000fb8c __mspabi_sral_5
0000fb90 __mspabi_sral_4
0000fb94 __mspabi_sral_3
0000fb98 __mspabi_sral_2
0000fb9c __mspabi_sral_1
0000fba2 __mspabi_slll_15
0000fba6 __mspabi_slll_14
0000fbaa __mspabi_slll_13
0000fbae __mspabi_slll_12
0000fbb2 __mspabi_slll_11
0000fbb6 __mspabi_slll_10
0000fbba __mspabi_slll_9
0000fbbe __mspabi_slll_8
0000fbc2 __mspabi_slll_7
0000fbc6 __mspabi_slll_6
0000fbca __mspabi_slll_5
0000fbce __mspabi_slll_4
0000fbd2 __mspabi_slll_3
0000fbd6 __mspabi_slll_2
0000fbda __mspabi_slll_1
0000fbe0 __mspabi_srll_15
0000fbe4 __mspabi_srll_14
0000fbe8 __mspabi_srll_13
0000fbec __mspabi_srll_12
0000fbf0 __mspabi_srll_11
0000fbf4 __mspabi_srll_10
0000fbf8 __mspabi_srll_9
0000fbfc __mspabi_srll_8
0000fc00 __mspabi_srll_7
0000fc04 __mspabi_srll_6
0000fc08 __mspabi_srll_5
0000fc0c __mspabi_srll_4
0000fc10 __mspabi_srll_3
0000fc14 __mspabi_srll_2
0000fc18 __mspabi_srll_1
0000fc1e __TI_decompress_none
0000fc5a INT_I2C_Analyze_NACK
0000fc8e ADC10_ISR
0000fcbc __mspabi_divi
0000fcbc __mspabi_remi
0000fce8 __mspabi_mpyl_f5hw
0000fd0a _c_int00_noargs_noexit
0000fd24 obt_init_Tx_UppMem05
0000fd3e obt_init_Rx_UppMem03
0000fd56 obt_init_Tx_UppMem03
0000fd6e __mspabi_divu
0000fd6e __mspabi_remu
0000fd84 __mspabi_mpyi_f5hw
0000fd9a write_to_fram
0000fdaa __TI_decompress_rle24
0000fdb8 __mspabi_srai
0000fdc2 __mspabi_slli
0000fdcc __mspabi_srli
0000fdd6 __TI_ISR_TRAP
0000fddc _system_pre_init
0000fde0 C$$EXIT
0000fde0 abort
0000ffce __TI_int31
0000ffd8 __TI_int36
0000ffde __TI_int39
0000ffe0 __TI_int40
0000ffe2 __TI_int41
0000ffe4 __TI_int42
0000ffe8 __TI_int44
0000ffea __TI_int45
0000ffec __TI_int46
0000ffee __TI_int47
0000fff0 __TI_int48
0000fff2 __TI_int49
0000fff4 __TI_int50
0000fff6 __TI_int51
0000fff8 __TI_int52
0000fffa __TI_int53
0000fffc __TI_int54
0000fffe _reset_vector
ffffffff __binit__
ffffffff __c_args__
ffffffff binit
UNDEFED __TI_INITARRAY_Base
UNDEFED __TI_INITARRAY_Limit
[659 symbols]
