Using XT1CLK but getting XCT1LFOFFG

Andy Bales22

Use: We need to drive the MSP with an external 29070 Hz 0-3V squarewave that is more accurate than REFOCLK.

Hardware: MSP-FET430UIF USB Debugger. TI MSP430PZ100B demo board.

What we are seeing is that the UCSCTL7 : XT1LFOFFG bit is always 1. It switches away from XCT1CLK to REFOCLK due to fault. We can setup the REFOCLK but its not stable enough for us. So we are trying to get the FLL to use the XTC1 source.

Here is the code I am using:

PMM_setVCore(PMM_CORE_LEVEL_3);
WDTCTL = WDTPW | WDTHOLD;   // not sure but stuck in anyway
__bis_SR_register(SCG0);               // Disable the FLL control loop
Bits16 ratio = 609;
UCSCTL6 &= ~(XT1OFF);                  // FAULT?  Turn on XCT1 external
UCSCTL1 = DCORSEL_6;                   // Select DCO range 20MHz operation
UCSCTL2 = ratio; //FLLD_1 | ratio;     // Set DCO Multiplier (FLLN, FLLD)  (32768 x 610 = 19,988,480 REFO, but not what we want exactly)
UCSCTL3 = FLLREFDIV_0;		       // Was 0x0020-> Now 0x0000, put on XT1CLK (not REFO) for FLL  FAULT?
__bic_SR_register(SCG0);     // Enable the FLL control loop
UCSCTL7 = 0;	                      // clear fault flags, fails
SFRIFG1 &= ~OFIFG;               // not sure but looks cool
__delay_cycles(625000);        // wait maybe work after stable?
SFRIFG1 &= ~OFIFG;
UCSCTL7 = 0;	                      // clear fault flags, fails
UCSCTL4 = SELA2 | SELS2 | SELM2;       // dcoclkdiv smclk & mclk & aclk, fails
UCSCTL7 = 0;	                      // clear fault flags, fails
//HACK END

Could it be the debugger or am I just doing it wrong? Trying all sorts of things, nothing good.

TIA.

over 11 years ago

0 Clemens Ladisch over 11 years ago

Guru 325980 points

Why aren't you using driverlib?

0 Andy Bales22 over 11 years ago in reply to Clemens Ladisch

Prodigy 210 points

I tried those as well - they fail even worse for me. They don't setup the MOD bits, DCORSEL bits either.

Not saying I am using them right though, just that they are failing for me. I even tried it without the debugger - UCS toggle calls P5.5 and P5.6 for XT1LFOFFG, DCOFFG bits if set later. They toggle with debugger, and w/o.

External 0-3V 29070 Hz sq wave applied to TI demo board. Looking for a 20MHz -> 29070 on MCLK, others.

PMM_setVCore(PMM_CORE_LEVEL_3);
WDTCTL = WDTPW | WDTHOLD;
WDT_A_hold(WDT_A_BASE);
UCS_setExternalClockSource(29070, 0);
UCSCTL1 = DCORSEL_6; // force valid dcorsel value, not 0!
UCS_LFXT1Start(UCS_XT1_DRIVE0, UCS_XCAP_0); // added??? Arb Gen doesn't need anything
UCS_bypassXT1(UCS_XT1_LOW_FREQUENCY);
UCS_clockSignalInit(UCS_FLLREF, UCS_XT1CLK_SELECT, UCS_CLOCK_DIVIDER_1);
UCS_initFLLSettle(29,688); // 610;//688
UCSCTL0 |=0x00F8; // force a MOD bit setup, not 0! otherwise you get a DCOFFG error
UCS_clockSignalInit(UCS_ACLK, UCS_DCOCLKDIV_SELECT, UCS_CLOCK_DIVIDER_1); // or UCS_DCOCLK_SELECT?
UCS_clockSignalInit(UCS_MCLK, UCS_DCOCLKDIV_SELECT, UCS_CLOCK_DIVIDER_1);
UCS_clockSignalInit(UCS_SMCLK, UCS_DCOCLKDIV_SELECT, UCS_CLOCK_DIVIDER_1);
UCSCTL7 = 0; //clear fault flags, but its not working anyways really...
XT1LFOFFG is always set from here out and REFO is really on MCLK now.

0 Clemens Ladisch over 11 years ago in reply to Andy Bales22

Guru 325980 points

It should never be necessary to poke at the UCSCTL registers when you are using driverlib.

Do not use UCS_LFXT1Start() when you do not have a crystal.

UCS_bypassXT1() waits for XT1LFOFFG to clear, so it wouldn't return if the external clock were not received correctly.

The parameters of UCS_initFLLSettle() are wrong; as far as I can tell, you want UCS_initFLLSettle(20000, 688) instead.

You probably want DCOCLK instead of DCOCLKDIV. (See section 5 of the User's Guide for an explanation what DCOCLKDIV is.)

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Using XT1CLK but getting XCT1LFOFFG