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MSP430F5438A: Storing data in flash memory: general question

S. L.
Intellectual 330 points

Hi,

I was reading a lot about using flash memory as data storage, but what I learned is, that many procedures are depending on the selected device. That's why I was opening this new topic, to clarify all my questions using the F5438A device.

What I know so far:

I can use the flash memory of the MSP to store user data. To do so, it's recommended to reserve memory in the linker file (*.xcl, I'm using IAR), so that the compiler doesn't save any other data in that particular memory range. To store data, I have to clear the segment I want to write, cause it's only possible to write from '1' to '0'. I found some code snipets for erasing and writing, they are working and I understand them. 

But now, we reach the borders of my knowledge ;) :

The User's Guide says, that during erasing it depends, whether the code is executed in RAM or Flash. I understood that, if the code for erasing the flash memory is executed in the flash, cpu is halted during this process. Running that particular code in RAM, CPU isn't halted. Ok, so far so good.

Now my questions:

1.  I can remember, that I read some time ago, that during erasing a segment I have to switch of all interrupts to protect flash cells being destroyed by a too long erasing interval. I don't find that information anymore... Is that right, or does the flash controller manage that on its own?

2. I wan't to do some data processing and communication tasks during the erase process, both of them depending on interrupts. Is that possible, by just initiating the erase cycle from RAM? In this case, if interrupts occur, are they executed although the ISR code is within (another) flash (bank)?

3. Is it an advantage if i reserve a full bank, or is it enough just sticking to segment borders while modifying the linker file?

Thanks so far for reading!

  • 0
    Guru 320660 points

    You can do flash erasing/writing from RAM, and it is possible to redirect the interrupt vectors to RAM by setting the SYSRIVECT bit, but section 7.3.3 of the User's Guide says:

    Interrupts are automatically disabled during any flash operation.

    During a bank erase, you can read other banks. This is not possible during segment erase or any writes.

  • 0 in reply to Clemens Ladisch
    Intellectual 330 points

    Thanks Clemens for your reply!

    I knew, that I read that information about interrupts somewhere in the User's Guide.. But it was like the needle in the haystack ;)

    I read in some other posts, that, as you said, it is possible to redirect the interrupts to RAM. But in combination with the information of section 7.3.3 I guess it doesn't work either?

  • 0 in reply to S. L.
    Guru 320660 points
    You cannot use actual interrupts while flashing. But you could poll the interrupt flags.
  • 0 in reply to Clemens Ladisch
    Intellectual 330 points
    After thinking again about that problem I figured out a last, maybe possible solution:
    If I reserve one complete bank only for my data, I can do a bank erase. During bank erase simultaneous code execution is possible (User's Guide Chapter 7.3).
    Are interrupts enabled in "read and fetch while erase" mode?
  • 0 in reply to S. L.
    Guru 320660 points

    The text I quoted says "any flash operation".

  • 0 in reply to Clemens Ladisch
    Intellectual 330 points

    Ok, I understand ;)

    I asked again, cause it is mentioned in chapter "flash memory access during write or erase" and I was not sure whether it is general or not. 

    As it seems to be general, maybe TI should state that at the beginning of chapter 7.3. That would make it more clear.

    Anyways, thank you for your answers Clemens!!

  • 0 in reply to S. L.
    Guru 227245 points
    S.L., you are partly right. Yes, during bank erase, code execution is possible. Except on a few MSPs where it is not and leads to a crash. However, the code must be (obviously) on a different bank than the one you erase. I never tested whether interrupts remain active or not (I always had them explicitly disabled). In theory, there is no reason why interrupts shouldn't work when erasing a different bank than bank0. After all, CPU and flash are independent, and reading an interrupt vector is no different from reading a data word or an instruction.

    Unfortunately, the 5438A is one of the MSPs with the bug. To do a bank erase, you need to initiate (and complete) the bank erase from within ram. See the 5438A errata sheet.
  • 0 in reply to Jens-Michael Gross
    Intellectual 330 points
    Thanks Jens-Michael,
    I will give it a try! Once I know, whether it's possible or not I will give a feedback.

    Just in this moment I fell over the flash bug ;)

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