Watchdog unexpected interval

Luis Afonso said:

I guess I have a broken MSP? :o

The MSP430x5xx and MSP430x6xx Family User's Guide says:

On devices that have XIN and XOUT shared with general-purpose I/O, XIN and XOUT pins are set to general-purpose I/Os and XT1 remains disabled until the I/O ports are configured for XT1 operation. If XIN and XOUT are not shared with general-purpose I/O, XT1 is enabled.

#include "driverlib.h"

void main(void)
{
    //Watchdog mode -> reset after expired time; WDT is clocked by ACLK
    //Set Watchdog Timer timeout 1s - SET BREAKPOINT HERE
    WDT_A_watchdogTimerInit(WDT_A_BASE,
                            WDT_A_CLOCKSOURCE_ACLK,
                            WDT_A_CLOCKDIVIDER_32K);

    WDT_A_start(WDT_A_BASE);

    //Set P1.0 to output direction
    GPIO_setAsOutputPin(
        GPIO_PORT_P1,
        GPIO_PIN0
        );

    //Toggle P1.0
    GPIO_toggleOutputOnPin(
        GPIO_PORT_P1,
        GPIO_PIN0
        );

    //Port select XT1
    GPIO_setAsPeripheralModuleFunctionInputPin(
        GPIO_PORT_P5,
        GPIO_PIN4 + GPIO_PIN5
        );

    //Initializes the XT1 crystal oscillator with no timeout
    //In case of failure, code hangs here.
    //For time-out instead of code hang use UCS_LFXT1StartWithTimeout()
    UCS_LFXT1Start(
        UCS_XT1_DRIVE0,
        UCS_XCAP_3
        );

    //Enter LPM3
    __bis_SR_register(LPM3_bits + GIE);
    //For debugger
    __no_operation();
}

Luis Afonso said:

If ACLK is sourced from XT1 in LF mode, an oscillator fault causes ACLK to be automatically switched to the REFO for its clock source (REFOCLK).

When using XT1 operation in LF mode as the reference source into the FLL (SELREF = {0}), a crystal fault automatically causes the FLL reference source, FLLREFCLK, to be sourced by the REFO.

Whereas section 16.2.5 Clock Fail-Safe Feature says:

The WDT_A provides a fail-safe clocking feature, ensuring the clock to the WDT_A cannot be disabled while in watchdog mode. This means that the low-power modes may be affected by the choice for the WDT_A clock.

If SMCLK or ACLK fails as the WDT_A clock source, VLOCLK is automatically selected as the WDT_A clock source.

- The watchdog uses VLOCLK as it's "fail-safe" clock source

- The FLL uses REFO as it's "fail-safe" clock source