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MSP-FET430UIF Signal tri state

Chad Lampros
Prodigy 10 points

Other Parts Discussed in Thread: MSP-FET

I’m using a 4-wire J-Tag connection with MSP-FET430UIF to program my MSP430 micro.  When I’m done programming the micro I need to open J-Tag connections or place them in a high impedance state.  First can the MSP-FET430-UIF do this?  I notice the chips on the MSP-FET430UIF controlling the signals are tri state.  Is the third state a high impedance state?  If so how do I tell the MSP-FET430UIF to place the signals in this high impedance state?  I’m using the MSP430.dll to communicate with the MSP-FET430-UIF.

 

Thanks You

Chad

  • 0
    Guru 34983 points

    Inside B36 section (MSP-FET) of slau278 MSP430 Hardware Tools User's Guide there is figure with pin states after power-up. All signals are in high dependance state except TEST (low) and RESET (high). There is no info inside slau278 about FET430-UIF, but I guess that pin states are the same, and that this can be found somewhere on ti e2e.

  • 0 in reply to zrno soli
    Guru 227245 points
    On FET430UIF, TCK and TMS are connected to VCCO with 4k7, TDI and TDO with 47k, and RST with 22k. VCCO is Pin2 of the connector and either programmed voltage or mirror of the sensed voltage on Pin4 of the JTAG connector. At FETUIF power-up, it likely is 0V (DAC output off by default), so a pull-down. Later a pull-up. (I didn't analyze the TPS76601 regulation circuit and the influence of DAC0 on it)
    So no real high-impedance here.

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